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SMP08FP PDF预览

SMP08FP

更新时间: 2024-01-11 12:28:49
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
8页 265K
描述
Octal Sample-and-Hold with Multiplexed Input

SMP08FP 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5.63放大器类型:SAMPLE AND HOLD CIRCUIT
JESD-30 代码:R-PDSO-G16端子数量:16
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
子类别:Sample and Hold Circuit表面贴装:YES
端子形式:GULL WING端子位置:DUAL
Base Number Matches:1

SMP08FP 数据手册

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SMP08–SPECIFICATIONS  
(@ VDD = +5 V, VSS = –5 V, DGND = 0 V, RL = No Load, TA = –40؇C to +85؇C for SMP08F,  
ELECTRICAL CHARACTERISTICS unless otherwise noted)  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Units  
Linearity Error  
Buffer Offset Voltage  
–3 V VIN +3 V  
TA = +25°C, VIN = 0 V  
–40°C TA +85°C, VIN = 0 V  
VIN = 0 V, TA = +25°C to +85°C  
0.01  
2.5  
3.5  
2.5  
%
VOS  
VHS  
10  
20  
4
5
20  
mV  
mV  
mV  
mV  
mV/s  
mA  
mA  
V
Hold Step  
V
IN = 0 V, TA = –40°C  
Droop Rate  
VCH/t  
ISOURCE  
ISINK  
TA = +25°C, VIN = 0 V  
2
Output Source Current  
Output Sink Current  
Output Voltage Range  
VIN = 0 V1  
1.2  
0.5  
–3.0  
VIN = 0 V1  
RL = 20 kΩ  
+3.0  
LOGIC CHARACTERISTICS  
Logic Input High Voltage  
Logic Input Low Voltage  
Logic Input Current  
VINH  
VINL  
IIN  
2.4  
V
V
µA  
0.8  
1
VIN = 2.4 V  
0.5  
DYNAMIC PERFORMANCE2  
Acquisition Time3  
tAQ  
tH  
tCH  
tDCS  
tIR  
TA = +25°C, –3 V to +3 V to 0.1%  
To ±1 mV of Final Value  
3.6  
1
90  
45  
90  
3
7
µs  
µs  
ns  
ns  
Hold Mode Settling Time  
Channel Select Time  
Channel Deselect Time  
Inhibit Recovery Time  
Slew Rate  
Capacitive Load Stability  
Analog Crosstalk  
ns  
SR  
V/µs  
pF  
dB  
<30% Overshoot  
–3 V to +3 V Step  
500  
–72  
SUPPLY CHARACTERISTICS  
Power Supply Rejection Ratio  
Supply Current  
PSRR  
IDD  
VS = ±5 V to ±6 V  
TA = +25°C  
–40°C TA +85°C  
60  
75  
4
5
dB  
mA  
mA  
7.5  
9.5  
(@ VDD = +12 V, VSS = 0 V, DGND = 0 V, RL = No Load, TA = –40؇C to +85؇C for SMP08F,  
unless otherwise noted)  
ELECTRICAL CHARACTERISTICS  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Units  
Linearity Error  
Buffer Offset Voltage  
60 mV VIN 10 V  
TA = +25°C, VIN = 6 V  
–40°C TA +85°C, VIN = 6 V  
VIN = 6 V, TA = +25°C to +85°C  
0.01  
2.5  
3.5  
2.5  
%
VOS  
VHS  
10  
20  
4
5
20  
mV  
mV  
mV  
mV  
mV/s  
mA  
mA  
V
Hold Step  
V
IN = 6 V, TA = –40°C  
Droop Rate  
VCH/t  
ISOURCE  
ISINK  
TA = +25°C, VIN = 6 V  
2
Output Source Current  
Output Sink Current  
Output Voltage Range  
VIN = 6 V1  
1.2  
0.5  
0.06  
0.06  
VIN = 6 V1  
R
L = 20 kΩ  
10.0  
9.5  
RL = 10 kΩ  
V
LOGIC CHARACTERISTICS  
Logic Input High Voltage  
Logic Input Low Voltage  
Logic Input Current  
VINH  
VINL  
IIN  
2.4  
V
V
µA  
0.8  
1
VIN = 2.4 V  
0.5  
DYNAMIC PERFORMANCE2  
Acquisition Time3  
tAQ  
TA = +25°C, 0 V to 10 V to 0.1%  
–40°C TA +85°C  
To ±1 mV of Final Value  
3.5  
3.75  
1
90  
45  
90  
4
500  
–72  
4.25  
6.00  
µs  
µs  
µs  
ns  
ns  
ns  
V/µs  
pF  
dB  
Hold Mode Settling Time  
Channel Select Time  
Channel Deselect Time  
Inhibit Recovery Time  
Slew Rate  
Capacitive Load Stability  
Analog Crosstalk  
tH  
tCH  
tDCS  
tIR  
SR  
R
L = 20 k4  
3
<30% Overshoot  
0 V to 10 V Step  
SUPPLY CHARACTERISTICS  
Power Supply Rejection Ratio  
Supply Current  
PSRR  
IDD  
10.8 V VDD 13.2 V  
TA = +25°C  
60  
75  
6.0  
dB  
mA  
8.0  
–40°C TA +85°C  
8.0  
10.0  
mA  
NOTES  
1Outputs are capable of sinking and sourcing over 20 mA but offset is guaranteed at specified load levels.  
2All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.  
3This parameter is guaranteed without test.  
4Slew rate is measured in the sample mode with 0 V to 10 V step from 20% to 80%.  
Specifications subject to change without notice.  
–2–  
REV. D  

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