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SMK2-67025EV-45SB PDF预览

SMK2-67025EV-45SB

更新时间: 2024-11-26 03:31:35
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
27页 528K
描述
Rad. Tolerant High Speed 8 Kb x 16 Dual Port RAM

SMK2-67025EV-45SB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:QFF, QFL84,1.2SQ
针数:84Reach Compliance Code:compliant
ECCN代码:3A001.A.2.CHTS代码:8542.32.00.41
风险等级:5.45最长访问时间:45 ns
I/O 类型:COMMONJESD-30 代码:S-XQFP-F84
JESD-609代码:e0长度:29.21 mm
内存密度:131072 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:16功能数量:1
端口数量:2端子数量:84
字数:8192 words字数代码:8000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:8KX16
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:QFF封装等效代码:QFL84,1.2SQ
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:2.89 mm最大待机电流:0.00002 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.26 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:29.21 mmBase Number Matches:1

SMK2-67025EV-45SB 数据手册

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Features  
Fast Access Time: 30/45 ns  
Wide Temperature Range: -55°C to +125°C  
Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility  
Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using  
More Than One Device  
On-chip Arbitration Logic  
Versatile Pin Select for Master or Slave:  
– M/S = H for Busy Output Flag On Master  
– M/S = L for Busy Input Flag On Slave  
INT Flag for Port to Port Communication  
Full Hardware Support of Semaphore Signaling Between Ports  
Fully Asynchronous Operation From Either Port  
Battery Back-up Operation: 2V Data Retention  
TTL Compatible  
Rad. Tolerant  
High Speed  
8 Kb x 16  
Single 5V + 10% Power Supply  
QML Q and V with SMD 5962-91617  
Dual Port RAM  
Introduction  
The M67025E is a very low power CMOS dual port static RAM organized as 8192 bit  
× 16. The product is designed to be used as a stand-alone 16-bit dual port RAM or as  
a combination MASTER/SLAVE dual port for 32-bit or more width systems. The Atmel  
MASTER/SLAVE dual port approach in memory system applications results in full  
speed, error free operation without the need of an additional discrete logic.  
M67025E  
Master and slave devices provide two independent ports with separate control,  
address and I/O pins that permit independent, asynchronous access for reads and  
writes to any location in the memory. An automatic power down feature controlled by  
CS permits the on-chip circuitry of each port in order to enter a very low stand by  
power mode.  
Using an array of eight transistors (8T) memory cell, the M67025E combines an  
extremely low standby supply current (typ = 1.0 µA) with a fast access time at 30 ns  
over the full temperature range. All versions offer battery backup data retention capa-  
bility with a typical power consumption at less than 5 µW.  
For military/space applications that demand superior levels of performance and reli-  
ability the M67025E is processed according to the methods of the latest revision of the  
MIL PRF 38635 (Q and V) and/or ESA SCC 9000.  
Rev. 4146J–AERO–06/03  
1

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