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SMK2-67025EV-45SV

更新时间： 2024-09-25 15:51:51
品牌 Logo 应用领域
TEMIC 静态存储器内存集成电路
页数 文件大小 规格书
23页 160K
描述
Dual-Port SRAM, 8KX16, 45ns, CMOS, 0.050 INCH, MQFP-84

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SMK2-67025EV-45SV 技术参数

生命周期：Transferred包装说明：0.050 INCH, MQFP-84
Reach Compliance Code：unknown风险等级：5.76
最长访问时间：45 ns其他特性：ON CHIP ARBITRATION LOGIC; SEMAPHORE SIGNALING
JESD-30 代码：S-XQFP-G84内存密度：131072 bit
内存集成电路类型：DUAL-PORT SRAM内存宽度：16
功能数量：1端子数量：84
字数：8192 words字数代码：8000
工作模式：ASYNCHRONOUS最高工作温度：125 °C
最低工作温度：-55 °C组织：8KX16
封装主体材料：UNSPECIFIED封装形状：SQUARE
封装形式：FLATPACK并行/串行：PARALLEL
认证状态：Not Qualified最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：GULL WING
端子位置：QUADBase Number Matches：1

SMK2-67025EV-45SV 数据手册

 浏览型号SMK2-67025EV-45SV的Datasheet PDF文件第2页浏览型号SMK2-67025EV-45SV的Datasheet PDF文件第3页浏览型号SMK2-67025EV-45SV的Datasheet PDF文件第4页浏览型号SMK2-67025EV-45SV的Datasheet PDF文件第5页浏览型号SMK2-67025EV-45SV的Datasheet PDF文件第6页浏览型号SMK2-67025EV-45SV的Datasheet PDF文件第7页 
M67025E  
8 K ꢀ 16 CMOS Dual Port RAM Rad Tolerant  
Introduction  
The M67025E is a very low power CMOS dual port static Using an array of eight transistors (8T) memory cell, the  
RAM organised as 8192 × 16. The M67025E is designed M67025E combines an extremely low standby supply  
to be used as a stand-alone 16 bit dual port RAM or as a current (typ = 1.0 µA) with a fast access time at 30 ns  
combination MASTER/SLAVE dual port for 32 bit or over the full temperature range. All versions offer battery  
more width systems. The TEMIC MASTER/SLAVE dual backup data retention capability with a typical power  
port approach in memory system applications results in consumption at less than 5 µW.  
full speed, error free operation without the need of an  
additional discrete logic.  
The M67025E is processed according to the methods of  
the latest revision of the MIL STD 883 (class B or S), ESA  
Master and slave devices provide two independant ports  
with separate control, address and I/O pins that permit  
independant, asynchronous access for reads and writes to  
any location in the memory. An automatic power down  
feature controlled by CS permits the on-chip circuitry of  
each port in order to enter a very low stand by power  
mode.  
SCC 9000 or QML.  
Features  
D Fast access time : 30, 45 ns  
D Versatile pin select for master or slave :  
– M/S = H for busy output flag on master  
– M/S = L for busy input flag on slave  
D Wide temperature range :  
–55 °C to +125 °C  
D Separate upper byte and lower byte control for multiplexed  
D INT flag for port to port communication  
D Full hardware support of semaphore signaling between ports  
D Fully asynchronous operation from either port  
D Battery back-up operation : 2 V data retention  
D TTL compatible  
bus compatibility  
D Expandable data bus to 32 bits or more using master/slave  
chip select when using more than one device  
D On chip arbitration logic  
D Single 5 V ± 10 % power supply  
1
Rev. F – June 30, 1999  
1234567...23

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