ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
D
Highest Performance Floating-Point Digital
Signal Processor (DSP) SMJ320C6701
– 7-, 6-ns Instruction Cycle Time
– 140-, 167-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– Up to 1 GFLOPS Performance
– Pin-Compatible With ’C6201 Fixed-Point
DSP
D
1M-Bit On-Chip SRAM
– 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
– 512K-Bit Dual-Access Internal Data
(64K Bytes)
D
D
32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
D
D
D
SMJ: QML Processing to MIL-PRF-38535
SM: Standard Processing
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
Operating Temperature Ranges
– Extended (W) –55°C to 115°C
– Extended (S) –40°C to 90°C
D
D
16-Bit Host-Port Interface (HPI)
– Access to Entire Memory Map
D
VelociTI Advanced Very Long Instruction
Word (VLIW) ’C67x CPU Core
– Eight Highly Independent Functional
Units:
Two Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– Four ALUs (Floating- and Fixed-Point)
– Two ALUs (Fixed-Point)
– Two Multipliers (Floating- and
Fixed-Point)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial-Peripheral-Interface (SPI)
Compatible (Motorola )
D
D
Two 32-Bit General-Purpose Timers
D
Instruction Set Features
– Hardware Support for IEEE
Single-Precision Instructions
– Hardware Support for IEEE
Double-Precision Instructions
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 32-Bit Address Range
– 8-Bit Overflow Protection
– Saturation
Flexible Phase-Locked-Loop (PLL) Clock
Generator
†
D
D
D
D
IEEE-1149.1 (JTAG )
Boundary-Scan-Compatible
429-Pin Ceramic Ball Grid Array (CBGA)
Package (GLP Suffix)
0.18-µm/5-Level Metal Process
– CMOS Technology
– Bit-Field Extract, Set, Clear
– Bit-Counting
– Normalization
3.3-V I/Os, 1.9-V Internal
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI is a trademark of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright 2001, Texas Instruments Incorporated
ꢌ ꢙ ꢤ ꢜ ꢛꢧ ꢢꢡ ꢟꢠ ꢡꢛ ꢝꢤ ꢦꢘ ꢞꢙ ꢟ ꢟꢛ ꢁꢏ ꢋꢒ ꢓꢕ ꢊ ꢒꢃꢮꢯ ꢃꢯꢰ ꢞꢦꢦ ꢤꢞ ꢜ ꢞ ꢝꢣ ꢟꢣꢜ ꢠ ꢞ ꢜ ꢣ ꢟꢣ ꢠꢟꢣ ꢧ
ꢢ ꢙꢦ ꢣꢠꢠ ꢛ ꢟꢩꢣ ꢜ ꢫꢘ ꢠꢣ ꢙ ꢛꢟꢣ ꢧꢨ ꢌ ꢙ ꢞꢦ ꢦ ꢛ ꢟꢩꢣ ꢜ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢠ ꢰ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛ ꢙ
ꢤ ꢜ ꢛꢡꢣ ꢠꢠꢘ ꢙꢭ ꢧ ꢛꢣꢠ ꢙ ꢛꢟ ꢙ ꢣꢡꢣꢠ ꢠꢞꢜ ꢘ ꢦꢬ ꢘ ꢙꢡꢦ ꢢ ꢧꢣ ꢟꢣꢠ ꢟꢘꢙ ꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝꢣ ꢟꢣꢜ ꢠ ꢨ
ꢓꢕ ꢌ ꢔꢗ ꢆ ꢎꢏ ꢌ ꢐ ꢔ ꢍꢎꢍ ꢘꢙ ꢚ ꢛꢜ ꢝ ꢞꢟ ꢘꢛꢙ ꢘꢠ ꢡꢢ ꢜ ꢜ ꢣꢙꢟ ꢞꢠ ꢛꢚ ꢤꢢꢥ ꢦꢘꢡ ꢞꢟ ꢘꢛꢙ ꢧꢞ ꢟꢣ ꢨ
ꢓꢜ ꢛ ꢧꢢꢡ ꢟ ꢠ ꢡ ꢛꢙ ꢚꢛ ꢜ ꢝ ꢟ ꢛ ꢠ ꢤꢣ ꢡ ꢘꢚ ꢘꢡꢞ ꢟꢘ ꢛꢙꢠ ꢤꢣ ꢜ ꢟꢩ ꢣ ꢟꢣ ꢜ ꢝꢠ ꢛꢚ ꢎꢣꢪ ꢞꢠ ꢏꢙꢠ ꢟꢜ ꢢꢝ ꢣꢙꢟ ꢠ
ꢠ ꢟ ꢞ ꢙꢧ ꢞ ꢜꢧ ꢫ ꢞ ꢜꢜ ꢞ ꢙ ꢟꢬꢨ ꢓꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛꢙ ꢤꢜ ꢛꢡ ꢣꢠ ꢠꢘ ꢙꢭ ꢧꢛꢣ ꢠ ꢙꢛꢟ ꢙꢣ ꢡꢣ ꢠꢠ ꢞꢜ ꢘꢦ ꢬ ꢘꢙꢡ ꢦꢢꢧ ꢣ
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ
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