Datasheet > SMC91C100

SMC91C100

更新时间： 2024-11-02 06:12:27

品牌	Logo	应用领域
其他 - ETC		控制器以太网
页数	文件大小	规格书
83页	413K
描述
FEAST Fast Ethernet Controller

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SMC91C100 数据手册

SMC91C100

ADVANCE INFORMATION

FEAST™

Fast Ethernet Controller

FEATURES

Dual Speed CSMA/CD Engine (10 Mbps and

100 Mbps)

Built-in Transparent Arbitration for Slave

Sequential Access Architecture

Flat MMU Architecture with Symmetric

Transmit and Receive Structures and

Queues

MII (Media Independent Interface) Compliant

MAC-PHY Interface (Compliant with

Emerging MII Standard Interface)

MII Management Serial Interface

Seven Wire Interface to 10 Mbps ENDEC

(SMC83C694)

Compliant with IEEE 802.3 100BASE-T

Specification

Supports 100BASE-TX, 100BASE-T4, and

10BASE-T Physical Interfaces

32 Bit Wide Data Path (Into Packet Buffer

Memory)

Support for 32 and 16 Bit Buses

Support for 32, 16 and 8 Bit CPU Accesses

Synchronous, Asynchronous and Burst DMA

Interface Mode Options

EEPROM-Based Setup

128 Kbyte External Memory

208 Pin QFP Package

GENERAL DESCRIPTION

The SMC91C100 FEAST is a high-speed network

controller designed to facilitate the implemetation of

Fast Ethernet adapters and connectivity products.

It contains a dual speed CSMA/CD engine that

implements the MAC portion of the CSMA/CD

protocol at 10 and 100 Mbps and couples it with a

lean and fast data and control path system

architecture to ensure data movement with no

bottlenecks at 100 Mbps.

efficient buffer utilization scheme, reducing software

tasks and relieving the host CPU from performing

these housekeeping functions. The total memory

size is 128 Kbytes (external), equivalent to a total

chip storage (transmit and receive) of 64

outstanding packets.

FEAST provides a flexible slave interface for easy

connectivity with industry-standard buses. The Bus

Interface Unit (BIU) can handle synchronous as well

as asynchronous buses, with different signals being

used for each one. FEAST's bus interface supports

synchronous buses like the VESA local bus, as well

as burst mode DMA for EISA environments.

Asynchronous bus support for ISA is supported

even though ISA cannot sustain 100 Mbps traffic.

Fast Ethernet could be adopted for ISA-

Memory management is handled using a unique

MMU (Memory Management Unit) architecture and

a 32-bit wide data path.

This I/O mapped

architecture can sustain back-to-back frame

transmission and reception for superior data

throughput and optimal performance. It also

dynamically allocates buffer memory in an

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与SMC91C100相关器件

型号	品牌	获取价格	描述	数据表
SMC91C94QFP	SMSC	获取价格	LAN Controller, 2 Channel(s), 1.25MBps, CMOS, PQFP100, QFP-100
SMC91C94TQFP	SMSC	获取价格	LAN Controller, 2 Channel(s), 1.25MBps, CMOS, PQFP100, TQFP-100
SMC91C95	ETC	获取价格	ISA/PCMCIA Full Duplex Single-Chip Ethernet and Modem Controller with RAM
SMC91CA	YANGJIE	获取价格	Trans Voltage Suppressor Diode, 77.8V V(RWM), Bidirectional
SMC9-65601L-30	TEMIC	获取价格	Standard SRAM, 1MX1, 30ns, CMOS, CDIP28,
SMC9-65601L-30:D	TEMIC	获取价格	Standard SRAM, 1MX1, 30ns, CMOS, CDIP28,
SMC9-65601L-30EHXXX	TEMIC	获取价格	Standard SRAM, 1MX1, 30ns, CMOS, CDIP28,
SMC9-65601L-30FHXXX:D	TEMIC	获取价格	Standard SRAM, 1MX1, 30ns, CMOS, CDIP28,
SMC9-65601L-30LHXXX	TEMIC	获取价格	Standard SRAM, 1MX1, 30ns, CMOS, CDIP28,
SMC9-65601L-30P883:D	TEMIC	获取价格	Standard SRAM, 1MX1, 30ns, CMOS, CDIP28,

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