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SM320DM6446

更新时间： 2024-11-04 11:58:19
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德州仪器 - TI /
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228页 1940K
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Digital Media System-on-Chip

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SM320DM6446 数据手册

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SM320DM6446  
Digital Media System-on-Chip  
www.ti.com  
SPRS607A–JUNE 2009–REVISED JUNE 2009  
1 Digital Media System-on-Chip (DMSoC)  
1.1 Features  
•
High-Performance Digital Media SoC  
•
ARM926EJ-S Core  
–
–
–
–
–
594-MHz C64x+™ Clock Rates  
297-MHz ARM926EJ-S™ Clock Rates  
Eight 32-Bit C64x+ Instructions/Cycle  
4752 C64x+ MIPS  
Fully Software-Compatible With C64x /  
ARM9™  
–
Support for 32-Bit and 16-Bit (Thumb®  
Mode) Instruction Sets  
DSP Instruction Extensions and Single  
Cycle MAC  
ARM® Jazelle® Technology  
EmbeddedICE-RT™ Logic for Real-Time  
Debug  
–
–
–
–
Extended Temperature Devices Available  
•
•
ARM9 Memory Architecture  
•
Advanced Very-Long-Instruction-Word (VLIW)  
TMS320C64x+™ DSP Core  
–
–
–
–
16K-Byte Instruction Cache  
8K-Byte Data Cache  
16K-Byte RAM  
–
Eight Highly Independent Functional Units  
•
Six ALUs (32-/40-Bit), Each Supports  
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit  
Arithmetic per Clock Cycle  
8K-Byte ROM  
Embedded Trace Buffer™ (ETB11™) With 4KB  
Memory for ARM9 Debug  
•
Two Multipliers Support Four 16 x 16-Bit  
Multiplies (32-Bit Results) per Clock  
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit  
Results) per Clock Cycle  
•
•
Endianness: Little Endian for ARM and DSP  
Video Processing Subsystem  
–
Front End Provides:  
–
Load-Store Architecture With Non-Aligned  
Support  
•
•
CCD and CMOS Imager Interface  
BT.601/BT.656 Digital YCbCr 4:2:2  
(8-/16-Bit) Interface  
–
–
–
–
64 32-Bit General-Purpose Registers  
Instruction Packing Reduces Code Size  
All Instructions Conditional  
•
•
Preview Engine for Real-Time Image  
Processing  
Glueless Interface to Common Video  
Decoders  
Additional C64x+™ Enhancements  
•
•
Protected Mode Operation  
Exceptions Support for Error Detection  
and Program Redirection  
•
•
Histogram Module  
Auto-Exposure, Auto-White Balance and  
Auto-Focus Module  
•
Hardware Support for Modulo Loop  
Operation  
•
Resize Engine  
•
C64x+ Instruction Set Features  
–
–
Resize Images From 1/4x to 4x  
Separate Horizontal/Vertical Control  
–
–
–
–
–
–
Byte-Addressable (8-/16-/32-/64-Bit Data)  
8-Bit Overflow Protection  
Bit-Field Extract, Set, Clear  
Normalization, Saturation, Bit-Counting  
Compact 16-Bit Instructions  
Additional Instructions to Support Complex  
Multiplies  
–
Back End Provides:  
•
•
Hardware On-Screen Display (OSD)  
Four 54-MHz DACs for a Combination of  
–
–
Composite NTSC/PAL Video  
Luma/Chroma Separate Video  
(S-video)  
•
C64x+ L1/L2 Memory Architecture  
–
Component (YPbPr or RGB) Video  
(Progressive)  
–
–
–
32K-Byte L1P Program RAM/Cache (Direct  
Mapped)  
80K-Byte L1D Data RAM/Cache (2-Way  
Set-Associative)  
64K-Byte L2 Unified Mapped RAM/Cache  
(Flexible RAM/Cache Allocation)  
•
Digital Output  
–
–
–
8-/16-bit YUV or up to 24-Bit RGB  
HD Resolution  
Up to 2 Video Windows  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this document.  
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009–2009, Texas Instruments Incorporated  
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