SM320DM642-HiRel
www.ti.com
SGUS063A–JUNE 2009–REVISED OCTOBER 2010
SM320DM642-HiRel
Video/Imaging Fixed Point Digital Signal Processor
Check for Samples: SM320DM642-HiRel
1 SM320DM642-HiRel Video/Imaging Fixed-Point Digital Signal Processor
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– Normalization, Saturation, Bit-Counting
– VelociTI.2™ Increased Orthogonality
• L1/L2 Memory Architecture
• Controlled Baseline
– One Assembly/Test/Fabrication Site
• Enhanced Diminishing Manufacturing Sources
(DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree(1)
• High-Performance Digital Media Processor
– 2 ns, 1.67 ns, 1.39 ns Instruction Cycle Time
– 128K Bit (16K Byte) L1P Program Cache
(Direct Mapped)
– 128K Bit (16K Byte) L1D Data Cache (2-Way
Set-Associative)
– 2M Bit (256K Byte) L2 Unified Mapped
RAM/Cache (Flexible RAM/Cache
Allocation)
– 720 MHz Clock Rate (500/600 MHz devices
are product preview only)
– Eight 32-Bit Instructions/Cycle
– 5760 MIPS
• Endianess: Little Endian, Big Endian
– 64 Bit External Memory Interface (EMIF)
– Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM, SBSRAM,
ZBT SRAM, and FIFO)
– Fully Software-Compatible With C64x™
• VelociTI.2™ Extensions to VelociTI™
Advanced Very Long Instruction Word (VLIW)
TMS320C64x™ DSP Core
• 1024M-Byte Total Addressable External
Memory Space
• Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
• 10/100 Mbps Ethernet MAC (EMAC)
– IEEE 802.3 Compliant
– Eight Highly Independent Functional Units
With VelociTI.2™ Extensions:
•
Six ALUs (32/40 Bit), Each Supports
Single 32 Bit, Dual 16 Bit, or Quad 8 Bit
Arithmetic per Clock Cycle
•
Two Multipliers Support Four 16 × 16-Bit
Multiplies (32 Bit Results) per Clock Cycle
or Eight 8 × 8 Bit Multiplies (16 Bit
Results) per Clock Cycle
– Media Independent Interface (MII)
– Eight Independent Transmit (TX) Channels
and One Receive (RX) Channel
• Management Data Input/Output (MDIO)
• Three Configurable Video Ports
– Load-Store Architecture With Non-Aligned
Support
– 64 32-Bit General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Provide a Glueless I/F to Common Video
Decoder and Encoder Devices
– Supports Multiple Resolutions/Video Stds
• VCXO Interpolated Control Port (VIC)
– Supports Audio/Video Synchronization
• Host Port Interface (HPI) [32/16 Bit]
• Instruction Set Features
– Byte Addressable (8/16/32/64 Bit Data)
– 8-Bit Overflow Protection
• 32 Bit/66 MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.2
– Bit Field Extract, Set, Clear
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
• Multichannel Audio Serial Port (McASP)
– Eight Serial Data Pins
– Wide Variety of I2S and Similar Bit Stream
Format
– Integrated Digital Audio I/F Transmitter
Supports S/PDIF, IEC60958-1, AES-3, CP-430
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
C64x, VelociTI.2, VelociTI, TMS320C64x, C6000, TMS320C6000, DM64x, C62x, TMS320C62x, TMS320C67x, Code Composer Studio,
DSP/BIOS, XDS, TMS320 are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
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