SLG46827-A
Auto Grade GreenPAK Programmable Mixed-Signal Matrix
with In-System Debug
Contents
General Description.................................................................................................................................................................1
Key Features.............................................................................................................................................................................1
Applications .............................................................................................................................................................................1
1 Block Diagram ......................................................................................................................................................................7
2 Pinout ....................................................................................................................................................................................8
2.1 Pin Configuration - TSSOP-20L .............................................................................................................................8
3 Characteristics ...................................................................................................................................................................12
3.1 Absolute Maximum Ratings .................................................................................................................................12
3.2 Electrostatic Discharge Ratings ...........................................................................................................................12
3.3 Recommended Operating Conditions ..................................................................................................................12
3.4 Electrical Characteristics ......................................................................................................................................13
3.5 Timing Characteristics .........................................................................................................................................21
3.6 OSC Characteristics .............................................................................................................................................26
3.7 ACMP Specifications ............................................................................................................................................26
3.8 Analog Temperature Sensor Characteristics .......................................................................................................30
4 In-System Debug ................................................................................................................................................................32
5 IO Pins .................................................................................................................................................................................33
5.1 IO Pins .................................................................................................................................................................33
5.2 GPIO Pins ............................................................................................................................................................33
5.3 GPO Pins .............................................................................................................................................................33
5.4 GPI Pins ...............................................................................................................................................................33
5.5 Pull-Up/Down Resistors .......................................................................................................................................33
5.6 Fast Pull-up/down during Power-up .....................................................................................................................33
5.7 I2C Mode IO Structure (VDD or VDD2) ...............................................................................................................34
5.8 Matrix OE IO Structure (VDD or VDD2) ...............................................................................................................35
5.9 Register OE IO Structure (VDD or VDD2) ...........................................................................................................36
5.10 Register OE IO Structure (VDD or VDD2) .........................................................................................................37
5.11 IO Typical Performance ....................................................................................................................................38
6 Connection Matrix ..............................................................................................................................................................40
6.1 Matrix Input Table ................................................................................................................................................41
6.2 Matrix Output Table .............................................................................................................................................42
6.3 Connection Matrix Virtual Inputs ..........................................................................................................................45
6.4 Connection Matrix Virtual Outputs .......................................................................................................................46
7 Combination Function Macrocells ....................................................................................................................................47
7.1 2-Bit LUT or D Flip-Flop Macrocells .....................................................................................................................47
7.2 2-bit LUT or Programmable Pattern Generator ....................................................................................................50
7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells .............................................................................................52
7.4 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell ..............................................................................................59
8 Multi-Function Macrocells .................................................................................................................................................64
8.1 3-Bit LUT or DFF/LATCH with 8-Bit Counter/Delay Macrocells ...........................................................................64
8.2 CNT/DLY/FSM Timing Diagrams .........................................................................................................................73
8.3 4-Bit LUT or DFF/LATCH with 16-Bit Counter/Delay Macrocell ...........................................................................82
8.4 Wake and Sleep Controller ..................................................................................................................................85
9 Analog Comparators ..........................................................................................................................................................89
9.1 ACMP0H Block Diagram .....................................................................................................................................90
9.2 ACMP1H Block Diagram .....................................................................................................................................91
9.3 ACMP2L Block Diagram .....................................................................................................................................92
9.4 ACMP3L Block Diagram .....................................................................................................................................93
9.5 ACMP Typical Performance .................................................................................................................................94
10 Programmable Delay/Edge Detector ..............................................................................................................................98
10.1 Programmable Delay Timing Diagram - Edge Detector Output .........................................................................98
11 Additional Logic Function. Deglitch Filter .....................................................................................................................99
12 Voltage Reference ..........................................................................................................................................................100
12.1 Voltage Reference Overview ...........................................................................................................................100
12.2 Vref Selection Table ........................................................................................................................................100
12.3 Vref Block Diagram .........................................................................................................................................101
Datasheet
24-Feb-2021
Revision 3.2
2 of 180
© 2021 Dialog Semiconductor
CFR0011-120-00
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