Datasheet > SLG46827-AGTR

SLG46827-AGTR

更新时间： 2022-06-24 15:43:10

品牌	Logo	应用领域
DIALOG		/
页数	文件大小	规格书
180页	2601K
描述
Auto Grade GreenPAK Programmable Mixed-Signal Matrix with In-System Debug

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数据手册

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SLG46827-AGTR 数据手册

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Block Diagram

IO11

ACMP3L

IO14

ACMP0H

IO13

ACMP1H

IO12

ACMP2L

IO10

Vref Out0

V_DD

Multiple Time

Programmable

Memory

I²C Serial

Communication

High Speed

Analog

In-System

Debug

Vref

Combination Function Macrocells

IO0

FILTER

with Edge

Detect

IO9

Vref Out1

ACMP0H

ACMP1H

2-bit

LUT2_0

or DFF0

LUT2_1

or DFF1

LUT2_2

or DFF2

LUT2_3

or PGEN

IO1

Temperature

Sensor

3bit

LUT3_0

or DFF3

3-bit

LUT3_1

or DFF4

3-bit

LUT3_2

or DFF5

3-bit

LUT3_3

or DFF6

V_DD2

Low Power

Analog

Low

Power

Vref

3-bit LUT3_6

or Pipe Delay

or Ripple

CNT

3-bit

LUT3_4

or DFF7

3-bit

LUT3_5

or DFF8

Programmable

Delay or Edge

Detect

IO2

IO8

ACMP2L

ACMP3L

Multi-Function Macrocells

3-bitLUT3_10

/DFF13+8bit

CNT/DLY4

3-bitLUT3_7

/DFF10+8bit

CNT/DLY1

3-bitLUT3_8

/DFF11+8bit

CNT/DLY2

3-bitLUT3_9

/DFF12+8bit

CNT/DLY3

IO3

IO7

Oscillators

POR

2.048

kHz

2.048

MHz

3-bit

4-bitLUT4_0

/DFF9+

3-bit

LUT3_11

LUT3_12

LUT3_13

/DFF14+8bit

CNT/DLY5

16bit

/DFF15+8bit

CNT/DLY6

/DFF16+8bit

CNT/DLY7

CNT/DLY0

IO4

GND

SDA

IO6

IO5

SCL

Figure 1: Block Diagram

Datasheet

24-Feb-2021

Revision 3.2

7 of 180

CFR0011-120-00

1...4 5 678 9 10...180

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