Datasheet > SL38000-15AH

SL38000-15AH

更新时间： 2024-11-13 01:09:59

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
10页	177K
描述
4-PLL Clock Generator with SSC

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SL38000-15AH 数据手册

SL38000-15AH

4-PLL Clock Generator with SSC

Key Features

Description

The SL38000-15AH a fully integrated 4 PLL low power

Clock Generator with a Spread Spectrum Clock (SSC)

function used for reducing Electromagnetic Interference

(EMI) and general purpose frequency synthesizing. The

product is designed using SpectraLinear proprietary phase-

locked loop (PLL) and SSC technology to synthesize and

modulate the input clock. The modulated clock can

significantly reduce the measured EMI levels, leading to the

compliance with regulatory agency requirements.

•

REFOUT=25.000MHz

CLK1=12.000MHz

CLK2=125.000MHz

SSCLK1=133.333MHz with +/-0.25% spread option

SSCLK2=50.000MHz with +0.5% spread option

VDD=VDDO=3.3V +/-10% power supply

25.000MHz external crystal

Integrated internal voltage regulator

PD# control function

SSCLK1 output provides +/-0.25% center-spread and

SSCLK2 output +0.5% up-spread. If SSON=1 both

spreads are on. Spreads can be turned off (no-spread) if

SSON=0.

OE control function (CLK1 only)

SSON enable/disable function function for

SSCLK1/2

The SL38000-15AH operates from 3.3V power supply.

•

Programmable CL at XIN and XOUT pins

Programmable output rise and fall times

The product is offered in 28-pin TSSOP package with both

commercial and industrial temperature grades available.

28-pin TSSOP package with commercial and

industrial temperature range available

Benefits

•

Eleminates the need for XOs and Xtals

EMI Reduction

Applications

•

Broadband Home Router

General Purpose Frequency Synthesising

Fast time-to-market

Cost Reduction

Reduction of PCB layers

Block Diagram

VDDO1/2/3

CLK1 (12.000MHz)

CLK2 (125.000MHz)

XIN

XTAL

OSCILLATOR

(XO)

PLL-1

PLL-2

XOUT

Output

SSCLK1 (133.333MHz)

Drivers with

Multi

Function I/O

SSCLK2 (50.000MHz)

Input Mux

and Control

Logic

and

REFOUT1 (25.000MHz)

Output

Drivers Drive

Strength

SS-PLL-3

SS-PLL-4

VDD

Control

Voltage

Regulators

To XO,

PLLs

PD#

SSON#

and Core

VSS

SS Logic

Control

Mux and Div

Control

MEMORY

Configuration

Logic

Rev 2.3, July 9, 2010

Page 1 of 10

www.silabs.com

400 West Cesar Chavez, Austin, TX 78701

1+(512) 416-8500

1+(512) 416-9669

12 3 4 5 6 7...10

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