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SL23EP04SC-1H PDF预览

SL23EP04SC-1H

更新时间: 2024-01-15 21:28:57
品牌 Logo 应用领域
芯科 - SILICON 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 969K
描述
PLL Based Clock Driver, 23EP Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, SOIC-8

SL23EP04SC-1H 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.19其他特性:ALSO OPERATES WITH 3.3V SUPPLY
系列:23EP输入调节:STANDARD
JESD-30 代码:R-PDSO-G8长度:4.889 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:8
实输出次数:4最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:1.727 mm
最大供电电压 (Vsup):2.75 V最小供电电压 (Vsup):2.25 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.8989 mm
Base Number Matches:1

SL23EP04SC-1H 数据手册

 浏览型号SL23EP04SC-1H的Datasheet PDF文件第2页浏览型号SL23EP04SC-1H的Datasheet PDF文件第3页浏览型号SL23EP04SC-1H的Datasheet PDF文件第4页浏览型号SL23EP04SC-1H的Datasheet PDF文件第5页浏览型号SL23EP04SC-1H的Datasheet PDF文件第6页浏览型号SL23EP04SC-1H的Datasheet PDF文件第7页 
SL23EP04  
Not Recommended for New Designs  
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)  
Key Features  
Description  
The SL23EP04 is a low skew, low jitter power  
Zero Delay Buffer (ZDB) designed to proto four  
(4) clock outputs from one (1) refeinput clock, for  
high speed clock distribution appons
10 to 220 MHz operating frequency range  
Low output clock skew: 60ps-typ  
Low output clock Jitter:  
Low part-to-part output skew: 150 ps-typ  
The product has an on-chip L and a feedback pin  
(FBK) which can be used feedback from any  
one of the 4 output clocks. 23EP04 offers X/2,1X  
and 2X frequency options at the output with respect to  
input reference clok. Refeto the “Product Coniguration  
Table” for the details of these options.  
3.3V to 2.5V power supply range  
Low power dissipation:  
- 12 mA-typ at 66MHz and VDD=3.3V  
- 10 mA-typ at 66MHz and VDD=2.5V  
One input drives 4 outputs  
The SL23E1H and -2H High Drive version operates  
up to 220 MHand 200MHz at 3.3 and 2.V power  
supples respectively. The standard sions -1 and -2  
operae up to 167MHz and 135MV and 2.5V  
ower supplies respectively with CF utput load.  
Multiple configurations and drive options  
SpreadThruPLL that allows use of SSCG  
Available in 8-pin SOIC package  
Available in Commercial and Industrial grades  
The SL23EP04 enter into Power Down (PD) mode if the  
input at CLKIN is DC (GND to VDD). In this state all 4  
output clocks are tri-stated and he PLL is turned off,  
leading to 8μA-typ r supply current draw.  
Applications  
Printers, MFPs and Digital Copiers  
PCs and Work Stations  
Routers, Switchers and Servers  
Datacom and Telecom  
Benefits  
4) distribution of input clock  
High-Speed Digital Embeded Sstems  
Std High-Drive levels to control  
impee level, frequency range and EMI  
Low skew, jitter and power dissipation  
Block Diagram  
FBK  
Low Power and  
Low Jitter  
PLL  
CLKA1  
CLKA2  
CLKIN  
(Divider for -2 only)  
/2  
CLKB1  
CLKB2  
VDD  
GND  
Rev 2.1, May 15, 2008  
2400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500  
Page 1 of 15  
www.silabs.com  
1+(512) 416-9669  

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