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SL23EP04SC-2HT PDF预览

SL23EP04SC-2HT

更新时间: 2024-02-12 16:07:54
品牌 Logo 应用领域
SPECTRALINEAR /
页数 文件大小 规格书
14页 164K
描述
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer(ZDB)

SL23EP04SC-2HT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.64Is Samacsys:N
其他特性:ALSO OPERATES WITH 3.3V SUPPLY系列:23EP
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
长度:4.889 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:8实输出次数:4
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.727 mm最大供电电压 (Vsup):2.75 V
最小供电电压 (Vsup):2.25 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.8989 mmBase Number Matches:1

SL23EP04SC-2HT 数据手册

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Preliminary  
SL23EP04  
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)  
Key Features  
Description  
The SL23EP04 is a low skew, low jitter and low power  
Zero Delay Buffer (ZDB) designed to produce up to four  
(4) clock outputs from one (1) reference input clock, for  
high speed clock distribution applications.  
x
x
x
10 to 220 MHz operating frequency range  
Low output clock skew: 60ps-typ  
Low output clock Jitter:  
- 35 ps-typ at 166MHz, CL=15pF and VDD=3.3V  
- 45 ps-typ at 166MHz, CL=15pF and VDD=2.5V  
Low part-to-part output skew: 150 ps-typ  
3.3V to 2.5V power supply range  
Low power dissipation:  
The product has an on-chip PLL and a feedback pin  
(FBK) which can be used to obtain feedback from any  
one of the 4 output clocks. The SL23EP04 offers X/2,1X  
and 2X frequency options at the output with respect to  
input reference clock. Refer to the “Product Configuration  
Table” for the details of these options.  
x
x
x
x
x
- 12 mA-typ at 66MHz and VDD=3.3V  
- 10 mA-typ at 66MHz and VDD=2.5V  
One input drives 4 outputs  
The SL23EP04-1H and -2H High Drive version operates  
up to 220 MHz and 200MHz at 3.3 and 2.5V power  
supplies respectively. The standard versions -1 and -2  
operate up to 167MHz and 135MHz at 3.3V and 2.5V  
power supplies respectively with CL=15pF output load.  
x
x
x
x
x
Multiple configurations and drive options  
SpreadThru™ PLL that allows use of SSCG  
Available in 8-pin SOIC package  
The SL23EP04 enter into Power Down (PD) mode if the  
input at CLKIN is DC (GND to VDD). In this state all 4  
output clocks are tri-stated and the PLL is turned off,  
leading to 8ȝA-typ power supply current draw.  
Available in Commercial and Industrial grades  
Applications  
Benefits  
x
x
x
x
x
Printers, MFPs and Digital Copiers  
PCs and Work Stations  
x
x
Up to four (4) distribution of input clock  
Routers, Switchers and Servers  
Datacom and Telecom  
Standard and High-Drive levels to control  
impedance level, frequency range and EMI  
x
Low skew, jitter and power dissipation  
High-Speed Digital Embeded Systems  
Block Diagram  
Rev 1.1, May 25, 2007  
Page 1 of 14  
2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com  

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