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SIT9120AI-1C1-25E133.333000T

更新时间： 2024-11-05 23:38:51
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13页 1141K
描述
-40 TO 85C, 5032, 20PPM, 2.5V, 1

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SIT9120AI-1C1-25E133.333000T 数据手册

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SiT9120  
Standard Frequency Differential Oscillator  
Features  
Applications  
31 standard frequencies from 25 MHz to 212.5 MHz  
LVPECL and LVDS output signaling types  
0.6 ps RMS phase jitter (random) over 12 kHz  
to 20 MHz bandwidth  
10GB Ethernet, SONET, SATA, SAS, Fibre Channel,  
PCI-Express  
Telecom, networking, instrumentation, storage, server  
Frequency stability as low as ±10 ppm  
Industrial and extended commercial temperature ranges  
Industry-standard packages: 3.2 x 2.5, 5.0 x 3.2 and  
7.0 x 5.0 mm x mm  
For any other frequencies between 1 to 625 MHz,  
refer to SiT9121 and SiT9122 datasheet  
Electrical Characteristics  
Table 1. Electrical Characteristics  
Parameters  
Symbol  
Min.  
Typ.  
Max.  
Unit  
Condition  
LVPECL and LVDS, Common Electrical Characteristics  
Supply Voltage  
Vdd  
2.97  
2.25  
2.25  
25  
3.3  
2.5  
–
3.63  
2.75  
3.63  
212.5  
+10  
+20  
+25  
+50  
+2  
V
V
V
Termination schemes in Figures 1 and 2 - XX ordering code  
See list of standard frequencies  
Output Frequency Range  
FrequencyStability  
f
–
MHz  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
°C  
F_stab  
-10  
-20  
-25  
-50  
-2  
–
Inclusive of initial tolerance, operating temperature,  
rated power supply voltage, and load variations  
–
–
–
First Year Aging  
F_aging1  
F_aging10  
T_use  
–
25°C  
10-year Aging  
–
+5  
25°C  
-5  
Operating TemperatureRange  
–
+85  
+70  
–
Industrial  
-40  
-20  
70%  
–
°C  
Extended Commercial  
Input Voltage High  
VIH  
VIL  
–
Vdd  
ST  
ST  
Pin 1, OE or  
Pin 1, OE or  
Input Voltage Low  
–
100  
–
30%  
250  
–
Vdd  
kΩ  
–
–
2
–
–
Input Pull-up Impedance  
Z_in  
ST  
Pin 1, OE logic high or logic low, or  
ST  
logic high  
MΩ  
ms  
Pin 1,  
logic low  
Start-up Time  
Resume Time  
T_start  
6
10  
Measured from the time Vdd reaches its rated minimum value.  
T_resume  
6
10  
ms  
ST  
In Standby mode, measured from the time  
50% threshold.  
pin crosses  
Duty Cycle  
DC  
–
55  
%
Contact SiTime for tighter dutycycle  
45  
LVPECL, DC and AC Characteristics  
Current Consumption  
Idd  
I_OE  
I_leak  
I_std  
–
–
–
–
61  
–
69  
35  
1
mA  
mA  
A  
Excluding Load Termination Current, Vdd = 3.3V or 2.5V  
OE Disable Supply Current  
Output Disable Leakage Current  
Standby Current  
OE = Low  
OE = Low  
–
–
100  
A  
ST  
= Low, for all Vdds  
Maximum Output Current  
Output High Voltage  
Output Low Voltage  
I_driver  
VOH  
Maximum average current drawn from OUT+ orOUT-  
See Figure 1(a)  
–
–
–
30  
Vdd-0.7  
Vdd-1.5  
2.0  
mA  
V
Vdd-1.1  
VOL  
Vdd-1.9  
–
V
See Figure 1(a)  
OutputDifferentialVoltageSwing  
Rise/Fall Time  
V_Swing  
Tr, Tf  
1.2  
–
1.6  
300  
–
V
See Figure 1(b)  
500  
ps  
ns  
ps  
ps  
ps  
ps  
20% to 80%, see Figure 1(a)  
OE Enable/Disable Time  
RMS Period Jitter  
T_oe  
–
115  
f = 212.5 MHz - For other frequencies, T_oe = 100ns + 3 period  
f = 100 MHz, VDD = 3.3V or 2.5V  
f = 156.25 MHz, VDD = 3.3V or 2.5V  
f = 212.5 MHz, VDD = 3.3V or 2.5V  
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdds  
T_jitt  
–
1.2  
1.2  
1.2  
0.6  
1.7  
–
1.7  
–
1.7  
RMS Phase Jitter (random)  
T_phj  
–
0.85  
Rev 1.08  
June 25, 2019  
www.sitime.com  
1234567...13

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