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SI5020 PDF预览

SI5020

更新时间: 2024-11-24 22:43:15
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描述
SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC

SI5020 数据手册

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Si5020  
SiPHY™ MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC  
Features  
Complete high speed, low power, CDR solution includes the following:  
! Supports OC-48/12/3, STM-16/4/1,  
!
!
Exceeds All SONET/SDH  
Jitter Specifications  
Gigabit Ethernet, and 2.7 Gbps FEC  
! Low Power—270 mW (TYP OC-48)  
! Small Footprint: 4 mm x 4 mm  
Jitter Generation  
3.0 mUIRMS (TYP)  
!
!
!
Device Power Down  
Loss-of-Lock Indicator  
Single 2.5 V Supply  
! DSPLL™ Eliminates External Loop  
Ordering Information:  
Filter Components  
! 3.3 V Tolerant Control Inputs  
See page 14.  
Applications  
Pin Assignments  
Si5020  
! SONET/SDH/ATM Routers  
! Add/Drop Multiplexers  
!
!
!
!
SONET/SDH Test Equipment  
Optical Transceiver Modules  
SONET/SDH Regenerators  
Board Level Serial Links  
! Digital Cross Connects  
! Gigabit Ethernet Interfaces  
20 19 18 17  
16  
Description  
PWRDN/CAL  
VDD  
REXT  
VDD  
1
2
3
4
5
15  
14  
13  
The Si5020 is a fully integrated low-power clock and data recovery (CDR)  
IC designed for high-speed serial communication systems. It extracts  
timing information and data from a serial input at OC-48/12/3, STM-16/4/1,  
or Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also  
provided for OC-48/STM-16 applications that employ forward error  
correction (FEC). DSPLL™ technology eliminates sensitive noise entry  
points thus making the PLL less susceptible to board-level interaction and  
helping to ensure optimal jitter performance.  
GND  
Pad  
DOUT+  
GND  
12 DOUT–  
11  
REFCLK+  
REFCLK–  
VDD  
6
7
8
9
10  
Top View  
The Si5020 represents a new standard in low jitter, low power, and small  
size for high speed CDRs. It operates from a single 2.5 V supply over the  
industrial temperature range (–40°C to 85°C).  
Functional Block Diagram  
LOL  
DSPLL™  
Phase-Locked  
Loop  
DIN+  
DIN–  
DOUT+  
DOUT–  
Retimer  
BUF  
BUF  
BUF  
2
2
2
PWRDN/CAL  
CLKOUT+  
CLKOUT–  
Bias  
2
2
RATESEL1–0  
REFCLK+  
REFCLK–  
REXT  
Preliminary Rev. 0.8 12/00  
Copyright © 2000 by Silicon Laboratories  
Si5020-DS08  
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.  

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