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SI3056SSI2-EVB PDF预览

SI3056SSI2-EVB

更新时间: 2024-11-23 03:43:23
品牌 Logo 应用领域
芯科 - SILICON /
页数 文件大小 规格书
94页 1395K
描述
GLOBAL SERIAL INTERFACE DIRECT ACCESS ARRANGEMENT

SI3056SSI2-EVB 数据手册

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Si3056  
Si3018/19/10  
GLOBAL SERIAL INTERFACE DIRECT ACCESS ARRANGEMENT  
Features  
Complete DAA includes the following:  
Programmable line interface  
Pulse dialing support  
Overload detection  
AC termination  
DC termination  
3.3 V power supply  
Ring detect threshold  
Ringer impedance  
Direct interface to DSPs  
Serial interface control for up to eight  
devices  
80 dB dynamic range TX/RX paths  
Integrated codec and 2- to 4-wire >5000 V isolation  
hybrid  
Proprietary isolation technology  
Parallel handset detection  
+3.2 dBm TX/RX level mode  
Programmable digital hybrid for near-  
end echo reduction  
Low-profile SOIC packages  
Lead-free/RoHS-compliant packages  
available  
Integrated ring detector  
Type I and II caller ID support  
Line voltage monitor  
Loop current monitor  
Polarity reversal detection  
Programmable digital gain  
Clock generation  
Ordering Information  
See page 88.  
Pin Assignments  
Si3056  
Applications  
MCLK  
FSYNC  
SCLK  
VD  
SDO  
SDI  
FC/RGDT  
RESET  
1
16  
OFHK  
RGDT/FSD/M1  
M0  
VA  
GND  
AOUT/INT  
C1A  
C2A  
2
3
4
5
6
15  
14  
13  
12  
11  
10  
9
V.92 modems  
Set-top boxes  
Internet appliances  
Personal digital  
assistants  
Voice mail systems Fax machines  
Multi-function printers  
Description  
7
8
The Si3056 is an integrated direct access arrangement (DAA) with a  
programmable line interface to meet global telephone line requirements. Available  
in two 16-pin small outline packages, it eliminates the need for an analog front end  
(AFE), isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. The  
Si3056 dramatically reduces the number of discrete components and cost  
required to achieve compliance with global regulatory requirements. The Si3056  
interfaces directly to standard modem DSPs.  
Si3018/19/10  
1
16  
15  
14  
13  
12  
11  
10  
9
DCT2  
IGND  
DCT3  
QB  
QE2  
SC  
QE  
DCT  
RX  
2
3
4
5
6
7
8
IB  
Functional Block Diagram  
C1B  
C2B  
VREG  
Si3056  
Si3018/19/10  
VREG2  
RNG2  
RNG1  
MCLK  
SCLK  
RX  
IB  
FSYNC  
Digital  
SC  
Interface  
SDI  
US Patent # 5,870,046  
US Patent # 6,061,009  
Other Patents Pending  
Hybrid and  
SDO  
FC/RGDT  
dc  
DCT  
Termination  
VREG  
VREG2  
DCT2  
DCT3  
Isolation  
Interface  
Isolation  
Interface  
RGDT/FSD/M1  
RNG1  
RNG2  
OFHK  
M0  
RESET  
Control  
Interface  
Ring Detect  
Off-Hook  
QB  
QE  
QE2  
AOUT/INT  
Rev. 1.05 6/05  
Copyright © 2005 by Silicon Laboratories  
Si3056  

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