Si3050+Si3011/18/19
PROGRAMMABLE VOICE DAA SOLUTIONS
Features
PCM highway data interface
TIP/RING polarity detection
Integrated codec and 2- to 4-wire
analog hybrid
µ-law/A-law companding
SPI control interface
GCI interface
80 dB dynamic range TX/RX
Line voltage monitor
Loop current monitor
+6 dBm or +3.2 dBm TX/RX level
mode
Parallel handset detection
3 µA on-hook line monitor current
Overload detection
Programmable line interface
AC termination
DC termination
Ring detect threshold
Ringer impedance
Programmable digital hybrid for
near-end echo reduction
Polarity reversal detection
Programmable digital gain in 0.1 dB
increments
Integrated ring detector
Type I and II caller ID support
Pulse dialing support
3.3 V power supply
Daisy-chaining for up to 16 devices
Greater than 5000 V isolation
Patented isolation technology
Ground start and loop start support
Available in Pb-free RoHS-compliant
packages
Ordering Information
See page 106.
Applications
DSL IADs
VoIP gateways
PBX and IP-PBX systems
Voice mail systems
DECT base stations
Package Options
Si3050
Description
CS
FSYNC
PCKLK
DTX
1
2
3
4
5
6
18
17
16
15
14
13
GND
VDD
VA
The Si3050+Si3011/18/19 Voice DAA chipset provides a highly-programmable
and globally-compliant foreign exchange office (FXO) analog interface. The
solution implements Silicon Laboratories' patented isolation capacitor technology,
which eliminates the need for costly isolation transformers, relays, or
opto-isolators, while providing superior surge immunity for robust field
performance. The Voice DAA is available as a chipset, a system-side device
(Si3050) paired with a line-side device (Si3011/18/19). The Si3050 is available in
a 20-pin TSSOP or a 24-pin QFN. The Si3011/18/19 is available in a 16-pin
TSSOP, a 16-pin SOIC, or a 20-pin QFN and requires minimal external
components. The Si3050 interfaces directly to standard telephony PCM
interfaces.
Si3050
Top View
C1A
DRX
C2A
GND
RGDT
RESET
Si3011/18/19
Functional Block Diagram
1
2
20
19
18
17 16
15 DCT3
Si3050
Si3018/19
NC
RX
IB
CS
SCLK
RX
Control
Data
Interface
3
4
14
13
QB
SDI
IB
SC
DCT
VREG
IGND
PAD
Hybrid, AC
and DC
Terminations
SDO
SDI THRU
QE2
C1B
C2B
VREG2
DCT2
PCLK
DTX
Isolation
Interface
Isolation
Interface
Line
Data
Interface
5
6
12 SC
11 NC
DCT3
DRX
7
8
9
10
RNG1
RNG2
QB
QE
QE2
FSYNC
Ring Detect
Off-Hook
RGDT
RG
Control
Logic
TGD
TGDE
RESET
AOUT/INT
US Patent# 5,870,046
US Patent# 6,061,009
Rev. 1.5 10/11
Copyright © 2011 by Silicon Laboratories
Si3050 + Si3011/18/19