Si3050 +
Si3018/19
GLOBAL VOICE DAA
Features
PCM highway data interface
µ-law/A-law companding
SPI control interface
GCI interface
80 dB dynamic range TX/RX
Line voltage monitor
Loop current monitor
+6 dBm or +3.2 dBm TX/RX level
mode
Parallel handset detection
3 µA on-hook line monitor current
Overload detection
Programmable line interface
AC termination
DC termination
TIP/RING polarity detection
Integrated codec and 2- to 4-wire
analog hybrid
Programmable digital hybrid for
near-end echo reduction
Polarity reversal detection
Programmable digital gain in 0.1 dB
increments
Integrated ring detector
Type I and II caller ID support
Pulse dialing support
3.3 V power supply
Daisy-chaining for up to 16 devices
Greater than 5000 V isolation
Patented isolation technology
Ground start and loop start support
Available in Pb-free RoHS-compliant
packages
Ring detect threshold
Ringer impedance
Ordering Information
See page 102.
Applications
DSL IADs
VoIP gateways
PBX and IP-PBX systems
Voice mail systems
Pin Assignments
Si3050
Description
SDITHRU
SCLK
SDO
SDI
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
The Si3050+Si3018/19 Voice DAA chipset provides a highly-programmable and
globally-compliant foreign exchange office (FXO) analog interface that is ideal for
DSL IADs, PBXs, IP-PBXs, and VoIP gateway products. The solution implements
Silicon Laboratories' patented isolation capacitor technology, which eliminates the
need for costly isolation transformers, relays, or opto-isolators, while providing
superior surge immunity for robust field performance. The Voice DAA is available
in one 20-pin TSSOP (Si3050) and one 16-pin TSSOP/SOIC (Si3018/19) and
requires minimal external components. The Si3050 interfaces directly to standard
telephony PCM interfaces.
CS
GND
VDD
FSYNC
PCLK
DTX
VA
C1A
C2A
RESET
DRX
RGDT
AOUT/INT
12 TGDE
11 TGD
RG 10
Functional Block Diagram
Si3018/19
Si3050
Si3018/19
1
16
15
14
13
12
11
10
9
DCT2
IGND
DCT3
QB
QE
CS
SCLK
RX
2
3
4
5
6
7
8
DCT
RX
Control
Data
Interface
SDI
IB
SC
DCT
VREG
Hybrid, AC
and DC
Terminations
SDO
IB
SDI THRU
C1B
C2B
VREG
RNG1
QE2
VREG2
DCT2
PCLK
DTX
Isolation
Interface
Isolation
Interface
SC
Line
Data
Interface
DCT3
VREG2
RNG2
DRX
RNG1
RNG2
QB
QE
QE2
FSYNC
Ring Detect
Off-Hook
RGDT
RG
Control
Logic
TGD
US Patent# 5,870,046
US Patent# 6,061,009
Other Patents Pending
TGDE
RESET
AOUT/INT
Rev. 1.31 5/09
Copyright © 2009 by Silicon Laboratories
Si3050 + Si3018/19