Si102x/3x
Ultra Low Power 128K, LCD MCU Family
Ultra Low Power at 3.6V
-
RF power consumption
18.5 mA receive
-
-
-
-
-
110 µA/MHz IBAT; DC-DC enabled
18 mA @ +1 dBm transmit
110 nA sleep current with data retention; POR monitor enabled
400 nA sleep current with smaRTClock (internal LFO)
700 nA sleep current with smaRTClock (external XTAL)
2 µs wake-up from any sleep mode
30 mA @ +13 dBm transmit
85 mA @ +20 dBm transmit
Data rate = 0.123 to 256 kbps
Auto-frequency calibration (AFC)
Antenna diversity and transmit/receive switch control
Programmable packet handler
TX and RX 64-byte FIFOs
12-Bit; 16 Ch. Analog-to-Digital Converter
-
-
-
Up to 75 ksps 12-bit mode or 300 ksps 10-bit mode
Frequency hopping capability
On-chip crystal tuning
External pin or internal VREF (no external capacitor required)
High-Speed 8051 µC Core
-
On-chip PGA allows measuring voltages up to twice the reference
voltage
Pipelined instruction architecture; executes 70% of instructions in 1
or 2 system clocks
-
-
Autonomous burst mode with 16-bit automatic averaging accumu-
lator
Integrated temperature sensor
Memory
-
Up to 128 kB Flash; In-system programmable; Full read/write/erase
functionality over the entire supply range
Up to 8 kB internal data RAM
Two Low Current Comparators
-
-
Programmable hysteresis and response time
Digital Peripherals
-
Configurable as interrupt or reset source
-
53 port I/O; All 5 V tolerant with high sink
current and programmable drive strength
Hardware SMBus™ (I2C™ compatible), 2 x SPI™, and UART
serial ports available concurrently
Internal 6-Bit Current Reference
-
Up to ±500 µA; source and sink capability
-
-
Enhanced resolution via PWM interpolation
Integrated LCD Controller (Si102x Only)
-
-
Four general-purpose 16-bit counter/timers
-
Supports up to 128 segments (32x4)
Programmable 16-bit counter/timer array with six capture/compare
modules and watchdog timer
-
Integrated charge pump for contrast control
Metering-Specific Peripherals
Clock Sources
-
-
DC-DC buck converter allows dynamic voltage scaling for
maximum efficiency (250 mW output)
Precision internal oscillators: 24.5 MHz with ±2% accuracy sup-
ports UART operation; spread-spectrum mode for reduced EMI
-
Sleep-mode pulse accumulator with programmable switch
de-bounce and pull-up control interfaces directly to metering sen-
sor
Dedicated Packet Processing Engine (DPPE) includes hardware
AES, DMA, CRC, and encoding blocks for acceleration of wireless
protocols
-
-
-
Low power internal oscillator: 20 MHz
External oscillator: Crystal, RC, C, CMOS clock
smaRTClock oscillator: 32.768 kHz crystal or 16.4 kHz internal
LFO with three independent alarms
-
-
On-Chip Debug
-
On-chip debug circuitry facilitates full-speed, non-intrusive, in-sys-
tem debug (no emulator required)
Provides 4 breakpoints, single stepping
Manchester and 3 out of 6 encoder hardware for power efficient
implementation of the wireless M-bus specification
-
EZRadioPRO® Transceiver
Packages
-
-
-
-
Frequency range = 240–960 MHz
-
–85 pin LGA (6 x 8 mm)
Sensitivity = –121 dBm
FSK, GFSK, and OOK modulation
Max output power = +20 dBm or +13 dBm
Port I/O Configuration
CIP-51 8051
Controller Core
128/64/32/16 kByte
ISP Flash Program
Memory
Power On
Reset/PMU
16
4
Port 0-1
Drivers
P0.0...P1.7
P2.4...P2.7
P3.0...P6.7
P7.0/C2D
Digital Peripherals
UART
Wake
Reset
Port 2
Drivers
Timers
32
Port 3-6
Drivers
Debug /
Programming
Hardware
0/1/2/3
C2CK/RST
256 Byte SRAM
Priority
Crossbar
PCA/
8192/4096 Byte XRAM
Port 7
Driver
Decoder
WDT
C2D
VBAT
VDD
DMA
SMBus
SPI 0
Analog
Power
CRC
Engine
VBAT
VDC
RF XCVR
(240-960 MHz,
+20/+13 dBm)
Digital
Power
Crossbar Control
LCD (4x32)
VREG
AES
Engine
PA
VCO
TX
Encoder
EMIF
SFR
Bus
VBATDC
IND
AGC
LNA
DC/DC Buck
Converter
SYSCLK
RXp
RXn
Pulse Counter
EZRadioPro SPI 1
Precision
24.5 MHz
Oscillator
GNDDC
Mixer
PGA
ADC
Low Power
20 MHz
Oscillator
Analog Peripherals
LCD Charge
Pump
CAP
Digital
Modem
External
VREF
Internal
VREF
External
Oscillator
Circuit
Delta
Sigma
Modulator
XTAL1
XTAL2
VDD
VREF
A
M
U
X
12-bit
Temp
Sensor
SDN
75ksps
ADC
Digital
Logic
Enhanced
smaRTClock
Oscillator
nIRQ
GPIOx
XTAL3
XTAL4
3
GND
GND
CP0, CP0A
+
-
30 MHz
XOUT
XIN
System Clock
Configuration
CP1, CP1A
+
-
Comparators
Rev. 0.3 11/11
Copyright © 2011 by Silicon Laboratories
Si102x/3x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
5秒后页面跳转
解析光耦仿真器：升级光耦合器技术的必要性
英伟达新一代Blackwell GPU过热问题致交付延迟
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
