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SG2525AP013TR PDF预览

SG2525AP013TR

更新时间: 2024-11-11 12:52:39
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 稳压器开关式稳压器或控制器电源电路开关式控制器脉冲光电二极管
页数 文件大小 规格书
12页 939K
描述
REGULATING PULSE WIDTH MODULATORS

SG2525AP013TR 技术参数

是否Rohs认证: 不符合生命周期:Active
零件包装代码:SOIC包装说明:SOP,
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:20 weeks风险等级:0.86
模拟集成电路 - 其他类型:SWITCHING CONTROLLER控制模式:VOLTAGE-MODE
控制技术:PULSE WIDTH MODULATION最大输入电压:35 V
最小输入电压:8 V标称输入电压:20 V
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm湿度敏感等级:3
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-25 °C
最大输出电流:0.5 A封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.75 mm
表面贴装:YES切换器配置:PUSH-PULL
最大切换频率:500 kHz温度等级:OTHER
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

SG2525AP013TR 数据手册

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SG2525A  
SG3525A  
®
REGULATING PULSE WIDTH MODULATORS  
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.
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.
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.
8 TO 35 V OPERATION  
5.1 V REFERENCE TRIMMED TO ± 1 %  
100 Hz TO 500 KHz OSCILLATOR RANGE  
SEPARATE OSCILLATOR SYNC TERMINAL  
ADJUSTABLE DEADTIME CONTROL  
INTERNAL SOFT-START  
PULSE-BY-PULSE SHUTDOWN  
INPUT UNDERVOLTAGE LOCKOUT WITH  
HYSTERESIS  
DIP16  
16(Narrow)  
.
LATCHING PWM TO PREVENT MULTIPLE  
PULSES  
DUAL SOURCE/SINK OUTPUT DRIVERS  
.
DESCRIPTION  
The SG3525A series of pulse width modulator inte-  
grated circuits are designed to offer improved per-  
formance and lowered external parts count when  
used in designing all types of switching power sup-  
plies. The on-chip + 5.1 V reference is trimmed to ±  
1 % and the input common-mode range of the error  
amplifier includes the reference voltage eliminating  
external resistors. A sync input to the oscillator al-  
lows multiple units to be slaved or a single unit to be  
synchronized to an external system clock. A single  
resistor between the CT and the discharge terminals  
provide a wide range of dead time ad- justment.  
These devices also feature built-insoft-startcircuitry  
with only an external timing capacitor required. A  
shutdown terminal controls both the soft-start circu-  
ity and the output stages, providing instantaneous  
turn off through the PWM latch with pulsed shut-  
down, as well as soft-start recycle with longer shut-  
down commands. These functions are also control-  
led by an undervoltage lockout which keeps the out-  
puts off and the soft-start capacitor discharged for  
sub-normal input voltages. This lockout circuitry in-  
cludes approximately 500 mV of hysteresis for jitter-  
free operation. Another feature of these PWM cir-  
cuits is a latch following the comparator. Once a  
PWM pulses has been terminated for any reason,  
the outputs will remain off for the duration of the pe-  
riod. The latch is reset with each clock pulse. The  
output stages are totem-pole designs capable of  
sourcing or sinking in excess of 200 mA. The  
SG3525A output stage features NOR logic, giving a  
LOW output for an OFF state.  
PIN CONNECTIONS AND ORDERING NUMBERS  
(top view)  
Type  
Plastic DIP  
SG2525AN  
SG3525AN  
SO16  
SG2525A  
SG3525A  
SG2525AP  
SG3525AP  
June 2000  
1/12  

SG2525AP013TR 替代型号

型号 品牌 替代类型 描述 数据表
SG2525AP STMICROELECTRONICS

类似代替

REGULATING PULSE WIDTH MODULATORS
SG3525AP STMICROELECTRONICS

类似代替

REGULATING PULSE WIDTH MODULATORS

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