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SG-8002CA40.0000M-PCML0:ROHS

更新时间： 2024-11-04 06:07:23
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精工 - SEIKO /
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描述
CMOS Output Clock Oscillator, 40MHz Nom, ROHS COMPLIANT, CERAMIC, SON-4

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SG-8002CA40.0000M-PCML0:ROHS 数据手册

 浏览型号SG-8002CA40.0000M-PCML0:ROHS的Datasheet PDF文件第2页 
Crystal oscillator  
Epson Toyocom  
Product Number (please contact us)  
SG-8002JF : Q3308JFx1xxxx00  
SG-8002CA : Q3309CAx0xxxx00  
CRYSTAL OSCILLATOR  
PROGRAMMABLE  
CA Type  
JF,CA Type  
SG-8002JF  
/
CA series  
•Frequency range  
•Supply voltage  
•Function  
:
:
:
1 MHz to 125 MHz  
3.3 V / 5.0 V  
Output enable(OE) or Standby( ST  
)
•External dimensions : 7.0 × 5.0 × 1.4 mm ···SG-8002CA  
•Pin compatible with ceramic package crystal oscillator (7 × 5)  
SG-8002JF  
Actual size  
SG-8002JF  
:
•Short mass production lead time by PLL technology.  
SG-8002CA  
•SG-Writer available to purchase.  
Please contact Epson Toyocom or local sales representative.  
Specifications (characteristics)  
Specifications *2  
PH / SH  
1 MHz to 125 MHz  
Item  
Symbol  
Remarks  
PT / ST  
PC / SC  
VCC=4.5 V to 5.5 V  
Output frequency range  
1 MHz to 125 MHz VCC=3.0 V to 3.6 V  
1 MHz to 66.7 MHz VCC=2.7 V to 3.6 V  
2.7 V to 3.6 V  
f
0
Supply voltage  
Storage  
VCC  
4.5 V to 5.5 V  
-55 °C to +125 °C  
Store as bare product after unpacking  
T_stg  
Temperature  
range  
temperature  
Operating  
-20 °C to +70 °C (-40 °C to +85 °C)  
-40 °C to +85 °C  
Refer to “Outline specifications” (Frequency range)  
T_use  
f_tol  
temperature  
B: ±50 × 10-6 ,C: ±100 × 10-6  
M: ±100 × 10-6  
45 mA Max.  
30 mA Max.  
50 μA Max.  
40 % to 60 %  
-20 °C to +70 °C  
-40 °C to +85 °C *3  
No load condition, Max. frequency range  
OE=GND(PT,PH,PC)  
Frequency tolerance  
Current consumption  
Disable current  
Stand-by current  
ICC  
I_dis  
I_std  
28 mA Max.  
16 mA Max.  
=GND(ST,SH,SC)  
ST  
CMOS load:50 % VCC level, Max. load condition  
TTL load: 1.4 V level, Max. load condition  
IOH=-16 mA(PT / ST,PH / SH),-8 mA(PC / SC)  
IOL=16 mA(PT / ST,PH / SH), 8 mA(PC / SC)  
f0≤90 MHz,Max. supply voltage  
Symmetry*1  
SYM  
40 % to 60 %  
High output voltage  
Low output voltage  
Output load condition (TTL) *1  
VOH  
VOL  
L_TTL  
VCC-0.4 V Min.  
0.4 V Max.  
5TTL Max.  
15 pF Max.  
15 pF Max.  
(CA:25 pF Max.)  
Output load condition (CMOS) *1  
L_CMOS  
15 pF Max.  
Max. frequency and Max. supply voltage  
Output enable / disable  
input voltage  
VIH  
VIL  
2.0 V Min.  
0.8 V Max.  
70 % VCC Min.  
20 % VCC Max.  
terminal or OE terminal  
ST  
3 ns Max.  
CMOS load: 20 % VCC to 80 % VCC level  
TTL load: 0.4 V to 2.4 V level  
Rise time / Fall time *1  
t
r / tf  
4 ns Max.  
10 ms Max.  
±5 × 10-6 / year Max.  
Time at minimum supply voltage to be 0 s  
+25 °C, VCC=5.0 V/ 3.3 V (PC / SC) First year  
Start-up time  
Frequency aging  
t_str  
f_aging  
*1 Operating temperature (-40 °C to +85 °C), the available frequency, symmetry and output load conditions, please refer to “Outline specifications” page.  
*2 PLL-PLL connection & Jitter specification, please refer to “Jitter specifications and characteristics chart” page.  
*3 PT / ST and PH / SH for “M” tolerance will be available up to 55 MHz. (JF:40 MHz)  
Checking possible by the Frequency Checking Program.  
External dimensions  
(Unit:mm)  
Footprint (Recommended) (Unit:mm)  
.
SG-8002JF  
7.1±0.2  
Note.  
OE Pin (PT, PH, PC)  
#4  
#3  
OE pin = "H" or "open" : Specified frequency output.  
OE pin = "L" : Output is high impedance.  
Pin map  
Pin  
1
Connection  
OE or ST  
GND  
OUT  
VCC  
E 125.00C  
ST pin (ST, SH, SC)  
2
3
4
2PH 9245A  
ST pin = "H" or "open" : Specified frequency output.  
ST pin = "L" : Output is low level (weak pull - down),  
oscillation stops.  
1.8  
C
#1  
(ex. 0.01 μF)  
#2  
0.4  
(0.75)  
3.8  
(0.75)  
5.08  
0 Min.  
Metal may be exposed on the top or bottom of this product. This will not affect any quality, reliability or electrical spec.  
Resist  
SG-8002CA  
1.4  
#3  
#4  
#3  
#4  
5.08  
E 125.000  
PHC935C  
#1  
#2  
7.0±0.2  
#1  
#2  
Pin map  
Pin  
1
5.08  
To maintain stable operation, provide a 0.01uF to  
0.1uF by-pass capacitor at a location as near as  
possible to the power source terminal of the  
crystal product (between Vcc - GND).  
Connection  
OE or ST  
GND  
2
3
4
OUT  
VCC  
5.08  
http://www.epsontoyocom.co.jp  
12

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