SC0010
588.235 MHz Differential Sine-Wave Clock
•
•
•
•
Quartz SAW Frequency Stability
Fundamental Fixed Frequency
Very Low Jitter and Power Consumption
Rugged, Hermetic, Metal DIP Case
DIP14S-8 Case
This digital clock is designed for use with high-speed CPUs and digitizers. Fundamen-
tal-mode oscillation is made possible by surface-acoustic-wave (SAW) technology. The
design results in low jitter, compact size, and low power consumption. Differential out-
puts provide a sine wave that is capable of driving 50 W loads.
Electrical Characteristics
Characteristic
Sym
fO
Notes
Minimum
Typical
Maximum
Units
Output Frequency
Q and Q Output
Absolute Frequency
588.117
588.352
±200
MHz
ppm
1, 2
DfO
VO
Tolerance from 588.235 MHz
Voltage into 50W (VSWR £ 1.2)
Operating Load VSWR
Symmetry
0.60
48
1.1
2:1
52
VP-P
1, 3
3, 4, 5
3, 4, 6
%
Harmonic Spurious
Nonharmonic Spurious
No Noise on VCC
-30
-60
30
dBc
dBc
psP-P
Q and Q Period Jitter
Output (Disabled)
3, 4, 6, 7
3, 4, 7, 8
3, 9
15
200 mVP-P from 1 MHz to ½ fO on VCC
psP-P
35
75
mVP-P
Amplitude into 50 W
3
50
VCC-0.1
0.0
KW
Output DC Resistance (between Q & Q)
VIH
VIL
IIH
VCC
VCC+0.1
0.20
5
ENABLE (Terminal 14)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Propagation Delay
Operating Voltage
Operating Current
V
V
3, 9
3
mA
mA
ms
VDC
mA
°C
IIL
-1
tPD
VCC
ICC
TA
1
DC Power Supply
+4.75
0
+5.0
25
+5.25
40
1, 3
1, 3
Operating Ambient Temperature
+70
Lid Symbolization (YY = Year, WW = Week)
RFM SC0019 588.23 MHz YYWW
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
Notes:
1. Unless otherwise noted, all specifications include any combination of load VSWR, VCC, and TA. In addition, Q and Q are terminated into 50 W loads
to ground. (See: Typical Test Circuit.)
2. One or more of the following United States patents apply: 4,616,197; 4,670,681; 4,760,352.
3. The design, manufacturing process, and specifications of this device are subject to change without notice.
4. Only under the nominal conditions of 50 W load impedance with VSWR £ 1.2 and nominal power supply voltage.
5. Symmetry is defined as the pulse width (in percent of total period) measured at the 50% points of Q or Q. (See: Timing Definitions.)
6. Jitter and other spurious outputs induced by externally generated electrical noise on VCC or mechanical vibration are not included. Dedicated exter-
nal voltage regulation and careful PCB layout are recommended for optimum performance.
7. Applies to period jitter of Q and Q. Measurements are made with the Tektronix CSA803 signal analyzer with at least 1000 samples.
8. Period jitter measured with a 200 mVP-P sine wave swept from 1 MHz to one-half of fO at the VCC power supply terminal.
9. The outputs are enabled when Terminal 8 is at logic HIGH. Propagation delay is defined as the time from the 50% point on the rising edge of
ENABLE to the 90% point on the rising edge of the output amplitude or as the fall time from the 50% point to the 10% point.
(SEE: Timing Definitions.)
RF Monolithics, Inc.
Phone: (972) 233-2903
Fax: (972) 387-8148
E-mail: info@rfm.com
http://www.rfm.com
SC0010-120298
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©1998 by RF Monolithics, Inc. The stylized RFM logo and RFM are registered trademarks of RF Monolithics, Inc.