Datasheet > S71WS128NB0BFWAM2

S71WS128NB0BFWAM2

更新时间： 2023-01-03 05:24:22

品牌	Logo	应用领域
飞索 - SPANSION		静态存储器
页数	文件大小	规格书
13页	331K
描述
Memory Circuit, Flash+PSRAM, 8MX16, CMOS, PBGA84, 8 X 11.60 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-84

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D a t a S h e e t

3. Input/Output Descriptions

Table 3.1 identifies the input and output package connections provided on the device.

Table 3.1 Input/Output Descriptions

Symbol

A23-A0

Description

Address inputs

DQ15-DQ0

OE#

Data input/output

Output Enable input. Asynchronous relative to CLK for the Burst mode.

WE#

Write Enable input.

Ground

No Connect; not connected internally

RDY

Ready output. Indicates the status of the Burst read. The WAIT# pin of the pSRAM is tied to RDY.

Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal

CLK

address counter. Should be at V or V while in asynchronous mode

Address Valid input. Indicates to device that the valid address is present on the address inputs.

Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched.

High = device ignores address inputs

AVD#

F-RST#

F-WP#

Hardware reset input. Low = device resets and returns to reading array data

Hardware write protect input. At V , disables program and erase functions in the four outermost sectors. Should be

at V for all other conditions.

Accelerated input. At V , accelerates programming; automatically places device in unlock bypass mode. At V

F-ACC

disables all program and erase functions. Should be at V for all other conditions.

R-CE1#

F1-CE#

F2-CE#

R-CRE

F-VCC

R-VCC

R-UB#

R-LB#

DNU

Chip-enable input for pSRAM.

Chip-enable input for Flash 1. Asynchronous relative to CLK for Burst Mode.

Chip-enable input for Flash 2. Asynchronous relative to CLK for Burst Mode. This applies to the 512Mb MCP only.

Control Register Enable (pSRAM). For CellularRAM only.

Flash 1.8 Volt-only single power supply.

pSRAM Power Supply.

Upper Byte Control (pSRAM).

Lower Byte Control (pSRAM)

Do Not Use

S71WS-N

S71WS-N_00_A7 April 4, 2008

1...3 4 567 8 9...13

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