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S71NS64JA0BJW12 PDF预览

S71NS64JA0BJW12

更新时间: 2024-10-29 07:33:23
品牌 Logo 应用领域
飞索 - SPANSION /
页数 文件大小 规格书
23页 525K
描述
Memory Circuit, 4MX16, CMOS, PBGA44, 9.20 X 8 MM, LEAD FREE, FBGA-44

S71NS64JA0BJW12 数据手册

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A d v a n c e I n f o r m a t i o n  
Contents  
Notice On Data Sheet Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii  
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8  
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Physical Dimensions–S71NS128JA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
NLA048—48-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 10 x 11 mm Package ...........................................10  
NLB044—44-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 9.2 x 8 mm Package ..........................................11  
Device History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Appendix B: Daisy Chain Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
pSRAM Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
pSRAM Device Bus Operations ...............................................................................................................................................16  
pSRAM DC Characteristics ......................................................................................................................................................16  
pSRAM AC Characteristics .......................................................................................................................................................16  
pSRAM Device Operation ......................................................................................................................................................... 17  
pSRAM Read Access ................................................................................................................................................................... 17  
pSRAM Write Access ................................................................................................................................................................. 17  
Configuration Register Access ................................................................................................................................................. 17  
Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Tables  
Table 1 Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Figures  
Figure 1 NLA048 Daisy Chain Layout (Top View, Balls Facing Down).................................................................................................... 14  
Figure 2 NLB044 Daisy Chain Layout (Top View, Balls Facing Down)..................................................................................................... 15  
Figure 3 Configuration Register Read Access.................................................................................................................................................. 18  
Figure 4 Configuration Register Write Access................................................................................................................................................. 18  
Figure 5 pSRAM Read Cycle 1 (WE# = VIH)..................................................................................................................................................... 19  
Figure 6 pSRAM Read Cycle 2 (WE# = VIH).................................................................................................................................................... 19  
Figure 7 pSRAM Write Cycle 1 (OE# = VIH)................................................................................................................................................... 20  
Figure 8 pSRAM Write Cycle 2 (OE# = VIH)................................................................................................................................................. 20  
2
S71NS128JA0/S71NS064JA0  
S71NS-JA0_00_A6 September22,2005  

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