S70FL01GS
1 Gbit (128 Mbyte) FL-S Flash
SPI Multi-I/O, 3.0 V
Features
• CMOS 3.0 V Core
• Serial peripheral interface (SPI) with Multi-I/O
- SPI clock polarity and phase modes 0 and 3
- Double data rate (DDR) option
- Extended addressing: 32-bit address
- Serial command set and footprint compatible with
S25FL-A, S25FL-K, and S25FL-P SPI families
- Multi I/O command set and footprint compatible with
S25FL-P SPI family
• READ commands
- Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
- AutoBoot – power up or reset and execute a Normal or Quad read command automatically at a preselected
address
- Common flash interface (CFI) data for configuration information
• Programming (1.5 Mbytes/s)
- 512-byte page programming buffer
- Quad-input page programming (QPP) for slow clock systems
• Erase (0.5 Mbytes/s)
- Uniform 256-kbyte sectors
• Cycling endurance
- 100,000 program-erase cycles, minimum
• Data retention
- 20-year data retention, minimum
• Security features
- One time program (OTP) array of 2048 bytes
- Block protection
• Status register bits to control protection against program or erase of a contiguous range of sectors.
• Hardware and software control options
• Advanced sector protection (ASP)
• Individual sector protection controlled by boot code or password
®
®
- Infineon 65 nm MirrorBit Technology with Eclipse™ architecture
- Core supply voltage: 2.7 V to 3.6 V
- I/O supply voltage: 1.65 V to 3.6 V
- Temperature range / grade:
• Industrial (−40°C to +85°C)
• Industrial Plus (−40°C to +105°C)
• Automotive, AEC-Q100 Grade 3 (−40°C to +85°C)
• Automotive, AEC-Q100 Grade 2 (−40°C to +105°C)
• Automotive, AEC-Q100 Grade 1 (−40°C to +125°C)
- Packages (all Pb-free)
• 16-lead SOIC (300 mils)
• BGA-24, 8 × 6 mm
• 5 × 5 ball (ZSA024) footprint
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1 of 22
001-98295 Rev. *O
2022-05-02