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S6E1B8

更新时间: 2024-11-07 00:49:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 微控制器
页数 文件大小 规格书
128页 1907K
描述
32-bit ARM® Cortex®-M0 FM0 Microcontroller

S6E1B8 数据手册

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PRELIMINARY  
S6E1B8 Series  
32-bit ARM® Cortex®-M0+  
FM0+ Microcontroller  
The S6E1B8 Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power  
consumption and low cost. This series has the ARM Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of  
peripheral functions such as various timers, LCD controller (LCDC), AES, ADC and communication interfaces (UART, CSIO (SPI),  
I2C, I2S, Smart Card, and USB). The products which are described in this data sheet are placed into TYPE2-M0+ product categories  
in "FM0+ Family Peripheral Manual".  
Features  
USB host  
USB 2.0 Full/Low-Speed supported  
32-bit ARM Cortex-M0+ Core  
Bulk-transfer, Interrupt-transfer and Isochronous-transfer  
Processor version: r0p1  
support  
Maximum operating frequency: 40.8 MHz  
USB Device connected/disconnected automatically detect  
IN/OUT token handshake packet automatically  
Max 256-byte packet-length supported  
Nested Vectored Interrupt Controller (NVIC): 1 NMI  
(non-maskable interrupt) and 24 peripheral interrupt with 4  
selectable interrupt priority levels  
Wake-up function supported  
24-bit System timer (Sys Tick): System timer for OS task  
LCD Controller (LCDC)  
Selectable from 44 SEG × 4 COM (Max) or 40 SEG × 8  
COM (Max)  
Internal Charge pump can generate 4.6 V at most  
Internal divide resistor is contained (selectable from 10 k  
or 100 kfor the resistor value)  
management  
Bit Band Operation  
Compatible with Cortex-M3 bit band operation.  
On-Chip Memory  
LCD drive power supply (bias) pin (VV4 to VV0)  
Interrupt function synchronized with the LCD module frame  
Flash memory  
Up to 512 K+48 Kbytes  
Dual bank:  
upper bank : 512 Kbytes(64 Kbytes x 8)  
lower bank : 48 Kbytes(8 Kbytes x 6)  
Read cycle: 0 wait-cycle  
Security function for code protection  
frequency  
With blinking function  
Inverted display function  
Multi-Function Serial Interface (Max 8channels)  
128 bytes with Tx/Rx FIFO in all channels (The number of  
FIFO steps varies depending on the settings of the  
communication mode or bit length.)  
SRAM  
The on-chip SRAM of this series has one independent SRAM .  
The operation mode of each channel can be selected from  
Up to SRAM: 60 K+4 Kbytes  
4Kbytes: can retain value in Deep Standby Mode  
one of the following.  
UART  
CSIO (CSIO is known to many customers as SPI)  
USB Interface  
I2C  
USB interface is composed of Device and Host  
PLL for USB is built-in, USB clock can be generated by  
multiplication of Main clock.  
UART  
Full duplex double buffer  
Parity can be enabled or disabled.  
Built-in dedicated baud rate generator  
External clock available as a serial clock  
Various error detection functions (parity errors, framing  
errors, and overrun errors)  
USB Device  
USB 2.0 Full-Speed supported  
Max 6 EndPoint supported  
EndPoint 0 is control transfer  
EndPoint 1, 2 can be selected Bulk-transfer,  
CSIO (also known as SPI)  
Interrupt-transfer or Isochronous-transfer  
Full duplex double buffer  
EndPoint 3 to 5 can select Bulk-transfer or  
Built-in dedicated baud rate generator  
Overrun error detection function  
Serial chip select function (ch1 and ch3 only)  
Data length: 5 to 16 bits  
Interrupt-transfer  
EndPoint 1 to 5 comprise Double Buffer  
The size of each EndPoint is according to the follows  
EndPoint 0, 2 to 5 : 64 bytes  
EndPoint 1 : 256 bytes  
Cypress Semiconductor Corporation  
Document Number: 001-99223 Rev.**  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 31, 2015  
 

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