Datasheet > S5T8555X01-L0B0

S5T8555X01-L0B0

更新时间： 2022-11-26 01:19:04

品牌	Logo	应用领域
三星 - SAMSUNG		/
页数	文件大小	规格书
10页	88K
描述
TIME SLOT ASSIGNMENT CIRCUIT

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S5T8555X01-L0B0 数据手册

S5T8555

TIME SLOT ASSIGNMENT CIRCUIT

APPLICATION CIRCUIT

The S5T8555 TSAC combined with any kind of 1 CHIP CODEC from S5T8554B/7B series can obtain data timing

as illustrated in Fig. 3. Even though FS output goes high before BCLK gets high, the D output of the 1 CHIP

CODEC remains in the TRI-STATE mode until both outputs are high.

The eight bit period is shortened to avoid PCM data clash at PCM pre-highway.

Alternatively, full 8 bits can be obtained by inverting the BCLK to the 1 CHIP CODEC devices, thereby rising edges

of BCLK and FS are aligned.

X/R

Fig. 4 is typical timing of the control data interface.

Fig. 5 is the typical application circuit at operating control mode 2.

BCLK

XSYC

FS_X1

FS_X2

D_X

TS_X

Figure 2. Transmit Data Timing

CLK_C

CH0, CH1

D_C

Figure 3. Control Data Timing

1...5 6 789 10

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