Datasheet > S4802

S4802

更新时间： 2024-09-23 03:34:19

品牌	Logo	应用领域
AMCC		异步传输模式 ATM
页数	文件大小	规格书
2页	405K
描述
SONET/SDH/ATM OC-48 Transceiver With CDR

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S4802 数据手册

Product Brief

S3155

PB1135_v1.01_05/09/03

SONET/SDH/ATM OC-48 Transceiver With CDR

The low jitter LVPECL interface is

compliant with the bit-error rate

requirements of the Telecodia and ITU-T

standards. The S3155 is packaged in a

196 PBGA, offering designers a small

package outline.

–

A t a G l a n c e

–

Features

•

650 mW typical power

Overview

Integrated clock data recovery

On-chip high-frequency PLL

for clock generation and clock

recovery

The S3155 transceiver implements

SONET/SDH serialization/deserializa-

tion, and transmission functions. This

chip can be used to implement the front

end of SONET equipment, which con-

sists primarily of the serial transmit inter-

face and the serial receive interface. The

chip handles all the functions of these

two elements, including parallel-to-serial

and serial-to-parallel conversion, clock

generation, and system timing. The

S3155 is divided into a transmitter sec-

tion and a receiver section. The

•

Supports OC-48 (2.488 Gbps)

with FEC

Reference frequency of 155.52

to 166.63 MHz

Description

•

RX and TX reference selectable

Interface to LVCMOS/LVTTL

logic

The S3155 SONET/SDH transceiver

chip is a fully integrated serialization/

deserialization SONET OC-48 (2.488 -

2.67 Gbps) interface device. The S3155

receives an OC-48 scrambled Non-

Return to Zero (NRZ) signal and

recovers the clock from the data. The

chip performs all necessary serial-to-

parallel and parallel-to-serial functions in

conformance with SONET/SDH

•

Internal input termination

option built-in

16-bit differential LVPECL/

LVDS data path or single-

ended LVPECL option

sequence of operations is as follows:

•

196 PBGA package

Transmitter Operations:

Diagnostic and line loopback

mode

1. 16-bit parallel input

2. Parallel-to-serial conversion

3. Serial output

transmission standards. The device is

suitable for SONET-based WDM

applications. The figure below shows a

typical network application.

•

Support serial loop timing

mode

•

Lock detect

Receiver Operations:

Signal detect input with polarity

select

On-chip clock synthesis is performed by

the high-frequency Phase-Locked Loop

(PLL) on the S3155 transceiver chip

allowing the use of a slower external

transmit clock reference. The chip can

be used with a 155.52 or 166.63 MHz

reference clock in support of existing

system clocking schemes.

1. Clock and data recovery from serial

input

•

Low Jitter LVPECL/LVDS

interface

2. Serial-to-parallel conversion

3. 16-bit parallel output

Internal FIFO to decouple

transmit clocks

ORX

OTX

ORX

S3155

Figure 1. System Block Diagram

Empowering Intelligent Optical Networks

中文翻译

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与S4802相关器件

型号	品牌	获取价格	描述	数据表
S4802CBI12	AMCC	获取价格	Support Circuit, 1-Func, CBGA624, CERAMIC, BGA-624
S4804	AMCC	获取价格	SONET/SDH/ATM OC-48 Transceiver With CDR
S4804CBI41	AMCC	获取价格	OC-48 / 4xOC-12 / 16xOC-3 SONET/SDH FRAMER AND POS/ATM MAPPER
S4805	AMCC	获取价格	SONET/SDH/ATM OC-48 Transceiver With CDR
S4805CBI11	AMCC	获取价格	Support Circuit, 1-Func, CBGA624, CERAMIC, BGA-624
S4806CBI	ETC	获取价格	STS-48/STM-16 SONET/SDH Framer and ATM/POS Mapper
S4810	HAMAMATSU	获取价格	Low-voltage operation photo IC Operation at low voltage from 2.2 V
S4810-100	HAMAMATSU	获取价格	Logic Output Photo IC, PLASTIC PACKAGE-3
S48-2225	ETC	获取价格	HIGH VOLTAGE SURFACE MOUNT MLCCS 250 - 5,000 VDC
S4825	HAMAMATSU	获取价格	Logic Output Photo IC, MINIATURE, PLASTIC PACKAGE-3

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