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S4804CBI41 PDF预览

S4804CBI41

更新时间： 2024-09-23 03:21:55
品牌 Logo 应用领域
AMCC 异步传输模式ATM
页数 文件大小 规格书
2页 42K
描述
OC-48 / 4xOC-12 / 16xOC-3 SONET/SDH FRAMER AND POS/ATM MAPPER

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中文翻译

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S4804CBI41 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：BGA,
针数：624Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.82
JESD-30 代码：S-CBGA-B624长度：32.5 mm
功能数量：1端子数量：624
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：BGA
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：5.672 mm标称供电电压：2.5 V
表面贴装：YES电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：INDUSTRIAL端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：32.5 mm
Base Number Matches：1

S4804CBI41 数据手册

 浏览型号S4804CBI41的Datasheet PDF文件第2页 
Part Number - S4804CBI41  
Product Brief Version 2.0 - January 2002  
PRODUCT BRIEF  
RHINE  
OC-48 / 4xOC-12 / 16xOC-3 SONET/SDH FRAMER AND POS/ATM MAPPER  
Features  
• Provides a SONET/SDH STS-48/STM-16, 4 STS-12/STM-  
4, or 16 STS-3/STM-1 line interfaces.  
The S4804 is a highly-integrated VLSI device that provides  
full-duplex mapping of packets or ATM cells to SONET/SDH  
payloads. It provides support for both uni-directional and  
bi-directional rings.  
• STS-48/STM-16 data stream supports a single STS-48c/  
AU-4-16c, or any valid combination of STS-12c/AU-4-4c  
and/or STS-3c/AU-4 SONET/SDH payloads.  
The S4804 provides full section, line, and path overhead  
processing, and supports framing, scrambling/descrambling,  
alarm signal insertion/detection, and bit-interleaved parity  
(B1/B2/B3) processing.  
• Each STS-12/STM-4 data stream supports a single STS-  
12c/AU-4-4c or 4 STS-3c/AU-4 SONET/SDH payloads.  
• Each STS-3/STM-1 data stream supports a single  
STS-3c/AU-4 SONET/SDH payload.  
The S4804 is SONET/SDH standards compliant with Bellcore  
GR-253, ITU G.707, ITU-T 432.1, ANSI T1.105 -1995, and  
IETF RFCs 1619/1661/1662/2615.  
• Supports mixed STS-3 / STS-12 line rates  
• Provides full-duplex mapping of ATM cells or packets in  
each payload tributary.  
A general purpose 8-bit or 16-bit microprocessor interface is  
provided for control and monitoring. The interface supports  
both IntelTM and MotorolaTM type microprocessors, and is  
capable of operating in either an interrupt-driven or  
polled-mode configuration. In addition, a standard 5 signal  
IEEE 1149.1 JTAG Test Port is provided for Boundary Scan  
test purposes.  
• Supports termination of mixed ATM and POS tributaries.  
• Terminates/generates SONET/SDH section, line, and path  
layers with transport/section E1, E2, F1, and DCC over-  
head interfaces in both transmit and receive directions.  
• APS port to support protection-switching configurations  
between two RHINE devices.  
Applications  
•
•
•
ATM switches  
• 16-bit, bus interface at 155 MHz for STS-48/STM-16 mode,  
or serial interfaces operating at 622/155 MHz for STS-12/3  
(STM-4/1) modes on the line side.  
Packet over SONET Routers and Switches  
SONET/SDH Add Drop Multiplexers, Terminal  
Multiplexers, and Digital Cross Connects  
• 32-bit, parallel interface (FlexBus-3TM) operating at 100  
MHz on the system side.  
•
Test equipment  
• .25 micron, 2.5V core, and 3.3V tolerant I/O.  
• Packaged in a 624 Pin CBGA.  
S4804CBI Block Diagram  
TX_ERR[1:4]  
TX_EOP[1:4]  
TX_LBYTE[1:0]  
TX_SYS_DAT[31:0]  
TX  
FIFO  
x16  
TX_ADR[4:0]  
TX_SONETCLK_OUT_155_622  
MICROPROCESSOR I/F  
TOH INSERT  
SPE/VC  
TX  
TX_CLK[1:4]  
TX_SONETCLK_OUT_155  
TX_PRTY[1:4]  
TX_ENB[1:4]  
FRAMER  
TX ATM/HDLC x16  
TX_DATA[15:0]  
TX_SONETCLK_IN  
TX_FRAME_IN  
x16  
PROC w/  
GEN.  
43  
(X + 1)  
SCRMBL  
x16  
TX_SOC/P[1:4]  
TX_CLAV_PDA[1:4]  
TX_CLK_OUT[1:4]  
RX_SYS_DAT[31:0]  
RX_ADR[4:0]  
RX ATM/HDLC  
PROC w/  
POH  
x16  
MON.  
43  
TOH  
MON.  
RX  
RX_DATA[15:0]  
x16  
(X + 1)  
DeSCRMBL  
x16  
FRAMER  
RX ATM/  
HDLC  
RX_SONETCLK[1:16]  
RX_CLK[1:4]  
RX_PRTY[1:4]  
RX_ENB[1:4]  
RX_SOC/P[1:4]  
RX_CLAV_PDA[1:4]  
RX_DV[1:4]  
x16  
Ptr  
Intrp  
Ptr  
Proc  
CNTRS  
x16  
RX_LOSEXT[1:16]  
RX_REF_CLK_OUT  
x16  
x16  
TOH EXTRACT  
JTAG PORT  
GPIO/LED REG  
RX  
FIFO  
x16  
RX_LBYTE[1:0]  
RX_EOP[1:4]  
RX_ERR[1:4]  
RX_CLK_OUT[1:4}  
Production Release Information - The information con-  
tained in this document is about a product in its fully tested  
and characterized phase. All features described herein are  
supported. Contact AMCC for updates to this document and  
the latest product status.  
AMCC  
12

中文翻译

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