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S4403B-66/TD PDF预览

S4403B-66/TD

更新时间: 2024-11-07 15:50:23
品牌 Logo 应用领域
AMCC 时钟信息通信管理外围集成电路晶体
页数 文件大小 规格书
13页 151K
描述
Clock Generator, 66MHz, BICMOS, PQCC44, PLASTIC, LCC-44

S4403B-66/TD 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:LCC
包装说明:QCCJ, LDCC44,.7SQ针数:44
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.88
Is Samacsys:NJESD-30 代码:S-PQCC-J44
JESD-609代码:e0长度:16.5481 mm
端子数量:44最高工作温度:70 °C
最低工作温度:最大输出时钟频率:66 MHz
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC44,.7SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V主时钟/晶体标称频率:66 MHz
认证状态:Not Qualified子类别:Clock Generators
最大压摆率:190 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:16.5481 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

S4403B-66/TD 数据手册

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®
DEVICE SPECIFICATION  
BiCMOS PLL CLOCK GENERATORS  
S4402/S4403  
FEATURES  
APPLICATIONS  
• Generates six clock outputs from 20 MHz to  
80 MHz (the S4403 generates ten outputs and  
HFOUT generates 10MHz to 40MHz)  
• CMOS ASIC Systems  
• High-speed Microprocessor Systems  
• Backplane Clock Deskew and Distribution  
• 21 selectable phase/frequency relationships for  
the clock outputs  
GENERAL DESCRIPTION  
• Compensates for clock skew by allowing output  
delay adjustment down to 3.125 ns increments  
The S4402/S4403 BiCMOS clock generators allow  
the user to generate multiphase TTL clocks in the  
10–80 MHz range with less than 400 ps of skew. Use  
of a single off-chip filter allows an entire 160–320  
MHz phase-locked loop (PLL) to be implemented on-  
chip. Divide-by-two and times-two outputs allow the  
ability to generate output clocks at half, equal to, or  
twice the reference clock input frequency. By using  
the programmable divider and phase selector, the  
user can select from up to 21 different output rela-  
tionships. The outputs can be phase-adjusted in in-  
crements as small as 3.125 ns to tailor the clocks to  
exact system requirements.  
• TTL outputs have less than 400 ps maximum  
skew  
• Lock Detect output indicates loop status  
• Internal PLL with VCO operating at 160 to  
320 MHz  
• Test Enable input allows VCO bypass for open-  
loop operation in board test  
• Maximum 1.0 ns of phase error (750 ps from  
part to part)  
• Proven 1.0 micron BiCMOS technology  
• Single +5V power supply operation  
• 28/44 PLCC packages  
Implemented in AMCC’s proven 1.0 micron BiCMOS  
technology, the S4402 generates six TTL outputs,  
while the S4403 provides those six plus four dupli-  
cates (FOUT0A–FOUT3A) for a total of ten. Output  
enables are provided for the various banks, allowing  
clock control for board and system tests.  
Figure 1. Clock Generator Block Diagram  
REFCLK  
PHASE  
DETECTOR  
LOCK  
CHARGE  
PUMP  
FBCLK  
FILTER  
NOTE: FOUT0A, FOUT1A,  
FOUT2A, FOUT3A, and  
OUTEN2 apply only to the  
S4403.  
X2FOUT  
VCO  
÷ 2  
HFOUT  
I
FOUT0A  
0
DIVIDER  
FOUT0  
I
1
AND  
MUX  
PHASE  
CONTROL  
LOGIC  
FOUT1A  
FOUT2A  
FOUT3A  
TSTEN  
SELECT  
FOUT1  
FOUT2  
FOUT3  
Digital  
+5V  
DIVSEL  
PHSEL0  
PHSEL1  
RESET  
0V  
OUTEN0  
OUTEN1  
Analog  
+5V  
0V  
OUTEN2  
Applied Micro Circuits Corporation  
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333  
Page 1  

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