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S32V234CO

更新时间： 2024-10-30 02:49:39
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
90页 1889K
描述
ARM Cortex-M4, 32-bit CPU 16 KB/16 KB I-/D- L1 Cache

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中文翻译

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S32V234CO 数据手册

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Document Number S32V234  
Rev. 9, 03/2020  
NXP Semiconductors  
Data Sheet: Technical Data  
S32V234  
S32V234 Data Sheet  
Features  
• Safety concept  
– ISO 26262, ASIL level target  
• ARM® Cortex®-A53, 64-bit CPU  
– Up to 1000 MHz Quad ARM Cortex-A53  
– 32 KB/32 KB I-/D- L1 Cache  
– NEON MPE co-processor  
– Measures to detect faults in memory and logic  
– Measures to detect single point and latent faults  
– Quantitative out of context analysis of functional  
safety (FMEDA) tailored to application specifics  
– Safety manual and FMEDA report available  
– Dual precision FPU  
– 2 clusters with 2 CPUs and 256 KB L2 cache each  
– Memory Management Unit  
• Security  
– GIC Interrupt Controller  
– ECC/parity error support for its memories  
– Generic timers  
– Fault encapsulation by hardware for redundant  
executed application software on multiple core  
cluster  
– CSE with 16 KB of on-chip Secure RAM and ROM.  
– ARM TrustZone (TZ) architecture support  
– Boot from NOR flash with AES-128 (CTR)  
– On-Chip One-Time Programmable element  
Controller (OCOTP_CTRL) with on chip electrical  
fuse array.  
– System JTAG Controller (SJC)  
• ARM Cortex-M4, 32-bit CPU  
– Up to 133 MHz  
• Debug functionality  
– 16 KB/16 KB I-/D- L1 Cache  
– 32+32 KB tightly coupled memory (TCM)  
– ECC/parity support for its memories  
– Standard JTAG and Compact JTAG  
– 16-bit Trace port, Serial Wire Output port  
• Timers  
• Clocks  
– General purpose timers (FTM)  
– Two Periodic Interrupt Timer (PIT)  
– IEEE 1588 Timers (part of Ethernet Subsystem)  
– Phase Locked Loops (PLLs)  
– 1 external crystal oscillator (FXOSC)  
– 1 FIRC oscillator  
• Analog  
• System protection and power management features  
– Flexible run modes to consume low power based on  
application needs  
– 1x 12-bit 1.8 V SAR ADC with self-test  
• Communications  
– UART(w/ LIN2.1l)  
– Serial peripheral interface (SPI)  
– I2C blocks  
– PCI express 2.0 with endpoint and root complex  
support  
– LFAST serial link  
– 1 GBit Ethernet with PTP IEEE 1588  
– FD-CAN  
– FlexRay Dual Channel, Version 2.1 RevA  
– Peripheral clock enable register can disable clocks to  
unused modules, thereby reducing currents  
– Power gating of unused A53 cores and GPU  
– Low and high voltage warning and detect  
– Hardware CRC module to support fast cyclic  
redundancy checks (CRC)  
– 120-bit unique chip identifier  
– Hardware watchdog  
– eDMA controller with 32 channels (with  
DMAMUX)  
– Extended Resource Domain Controller  
NXP reserves the right to change the production detail specifications as may be  
required to permit improvements in the design of its products.  
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 		Fixed Resistor, Wire Wound, 3W, 3.48ohm, 150V, 0.01% +/-Tol, -50,50ppm/Cel, Surface Mount,

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