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S3031

更新时间： 2024-01-28 17:29:06
品牌 Logo 应用领域
AMCC 电信集成电路异步传输模式ATM
页数 文件大小 规格书
26页 245K
描述
E4/STM-1/OC-3 ATM TRANSCEIVER

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S3031 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：QFP,针数：100
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.82JESD-30 代码：R-PQFP-G100
长度：20 mm功能数量：1
端子数量：100最高工作温度：85 °C
最低工作温度：-20 °C封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装形状：RECTANGULAR
封装形式：FLATPACK认证状态：Not Qualified
座面最大高度：2.35 mm标称供电电压：5 V
表面贴装：YES电信集成电路类型：ATM/SONET/SDH TRANSCEIVER
温度等级：OTHER端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

S3031 数据手册

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®
DEVICE  
SPECIFICATION
S3031B  
E4/STM-1/OC-3 ATM TRANSCEIVER  
GENERAL DESCRIPTION  
FEATURES  
•
•
•
•
•
•
Complies with Bellcore and ITU-T  
specifications  
On-chip high-frequency PLLs for clock  
generation and clock recovery  
On-chip analog circuitry for transformer  
driver and equalization  
Supports 139.264 Mbps (E4) and 155.52  
Mbps (OC-3) transmission rates  
Supports 139.264 Mbps and 155.52 Mbps  
Coded Mark Inversion (CMI) interfaces  
TTL Reference frequencies of 19.44 and  
38.88 MHz (OC-3) or 17.408 and 34.816  
MHz (E4)  
Interface to both PECL and TTL logic  
Lock detect on clock recovery function —  
monitors run length and frequency  
Serial and 4 bit (nibble) system interfaces  
Low jitter PECL interface  
The S3031B transceiver chip is a fully integrated CMI  
encoding transmitter and CMI decoding receiver. The  
chip derives high speed timing and data signals for  
SONET/SDH or PDH-based equipment. The circuit is  
implementedusingAMCC’sprovenPhaseLockedLoop  
(PLL) technology. Figures 1a and 1b show typical  
network applications.  
The S3031B has two independent VCOs which are  
synchronized to the local NRZ transmitted data and the  
received CMI data respectively. The chip can be used  
with either a 19.44 MHz or a 38.88 MHz reference clock  
when operated in the SONET/SDH OC-3 mode. In E4  
mode the chip can be operated with a 17.408 MHz or a  
34.816 MHz reference in support of existing system  
clockingschemes.On-chipcoded-mark-inversion(CMI)  
encoding and decoding is provided for 139.264 Mbps  
and 155.52 Mbps interfaces.  
•
•
•
•
•
•
•
+5V operation  
100 PQFP/TEP package  
Supports both electrical and optical interfaces  
The low jitter PECL interface for the serial data inputs  
and the PECL nibble clock interface guarantee com-  
pliancewiththebit-errorraterequirementsoftheBellcore  
and ITU-T standards. The S3031B is packaged in a  
0.65 mm pitch 100-pin PQFP/TEP.  
APPLICATIONS  
•
•
ATM over SONET/SDH  
OC-3/STM-1 or E4-based transmission  
systems  
OC-3/STM-1 or E4 modules  
OC-3/STM-1 or E4 test equipment  
Section repeaters  
Add Drop Multiplexers (ADM)  
Broadband cross-connects  
Fiber optic terminators  
The S3031B provides the major active components on-  
chip for a coaxial cable interface, including analog  
transformer driver circuitry and equalization interface  
circuitry. Discrete controls permit separate selection of  
CMI or NRZ operation and analog (coaxial copper) or  
PECL (optical module) media interfaces. Both line  
loopback and diagnostic local loopback operation are  
supported.  
•
•
•
•
•
•
•
Fiber optic test equipment  
Figure 1a. Electrical Interface  
139.264/155.52 Mbps CMI  
139.264/155.52 Mbps CMI  
COAX  
COAX  
139.264/155.52 Mbps NRZ  
139.264/155.52 Mbps NRZ  
17.408/19.44 MHz  
E4/STM-1/OC-3  
OVERHEAD  
PROCESSOR  
XFMR  
XFMR  
S3031B  
XCVR  
OSC  
Figure 1b. Optical Interface  
139.264/155.52 Mbps NRZ  
139.264/155.52 Mbps NRZ  
139.264/155.52 Mbps  
E4/STM-1/OC-3  
OVERHEAD  
PROCESSOR  
OTX  
S3031B  
XCVR  
139.264/155.52 Mbps  
ORX  
17.408/19.44 MHz  
OSC  
1
August 19, 1999 / Revision D  
1234567...26

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