Datasheet > S3032QF

S3032QF

更新时间： 2024-02-15 15:28:20

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Telecom IC

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S3032QF 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.7
Base Number Matches：	1

S3032QF 数据手册

Part Number S3032

Revision 1.0 - January 17, 2000

APPLICATION NOTE

S3032

Board Decoupling Guidelines

SONET/SDH/ATM OC-3/12 Transceiver w/CDR S3032 Example

The S3032 transceiver chip is a fully integrated serialization/deserialization SONET OC-12 (622.08 Mbit/s) and

OC-3 (155.52 Mbit/s) interface device. Figure 1 illustrates the connections for the S3032 device. External capaci-

tors are required for power supply decoupling only. Inductors are Murrata BLM31B601SPB or BLM11B601SPB

surface mount ferrites. The double capacitors shown are parallel 0.1 mF X7R and 100 pF are COG or NPO ceramic

chip. The CAP1/CAP2 capacitor should be 0.01 mF X7R. Note that 100 pF should be placed on the top side of the

board near the decoupled pin, and the 0.1 mF should be placed on the bottom side of the board for better capacitor

efficiency. The Low ESR 10 mF capacitors and 0 W resistors are optional for AVCC, for higher noise environments.

Figure 1. S3032 Connections

0.1 mF

100

TTLVCC 48

0.1 mF

PCLKGND

TXCOREGND

TXCOREVCC

TTLVCC 46

0.1 mF

S3032

Pinout

(Optional)

0 W

TTLGND

AVCC1

AGND1

CAP2

100 pF

10 mF

(Optional)

Top View

64 pin PQFP

0.01 mF

CAP1

0.1 mF

TTLVCC 38

AGND0

0.1 mF

12 AVCC0

100 pF

TXOUTVCC

100

0.1 mF

TTLGND

100 pF

0.1 mF

100 pF

0.1 mF

10 mF (Optional)

0 W (Optional)

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