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S29WS064J1ABAW00 PDF预览

S29WS064J1ABAW00

更新时间: 2024-02-08 12:42:10
品牌 Logo 应用领域
飞索 - SPANSION 内存集成电路
页数 文件大小 规格书
110页 2013K
描述
Flash, 4MX16, 45ns, PBGA80, 7 X 9 MM, FBGA-80

S29WS064J1ABAW00 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:BGA包装说明:7 X 9 MM, FBGA-80
针数:80Reach Compliance Code:compliant
ECCN代码:3A991.B.1.AHTS代码:8542.32.00.51
风险等级:5.8Is Samacsys:N
最长访问时间:45 ns其他特性:SYNCHRONOUS BURST MODE OPERATION ALSO POSSIBLE
启动块:BOTTOM/TOPJESD-30 代码:R-PBGA-B80
JESD-609代码:e0长度:9 mm
内存密度:67108864 bit内存集成电路类型:FLASH
内存宽度:16功能数量:1
端子数量:80字数:4194304 words
字数代码:4000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-25 °C
组织:4MX16封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240编程电压:1.8 V
认证状态:Not Qualified座面最大高度:1 mm
最大供电电压 (Vsup):1.95 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:TIN LEAD端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30类型:NOR TYPE
宽度:7 mmBase Number Matches:1

S29WS064J1ABAW00 数据手册

 浏览型号S29WS064J1ABAW00的Datasheet PDF文件第2页浏览型号S29WS064J1ABAW00的Datasheet PDF文件第3页浏览型号S29WS064J1ABAW00的Datasheet PDF文件第4页浏览型号S29WS064J1ABAW00的Datasheet PDF文件第5页浏览型号S29WS064J1ABAW00的Datasheet PDF文件第6页浏览型号S29WS064J1ABAW00的Datasheet PDF文件第7页 
S29WS128J/064J  
128/64 Megabit (8/4 M x 16-Bit)  
CMOS 1.8 Volt-only Simultaneous Read/Write,  
Burst Mode Flash Memory  
ADVANCE  
INFORMATION  
Distinctive Characteristics  
Architectural Advantages  
Performance Charcteristics  
„
Single 1.8 volt read, program and erase (1.65 to  
1.95 volt)  
„
Read access times at 104/80/66 MHz  
— Burst access times of 7.0/9.1/11.2 ns @ 30 pF at  
industrial temperature range  
„
„
Manufactured on 0.11 µm process technology  
— Synchronous latency of 45.5/46/56 ns (at 30 pF)  
VersatileIO™ (VIO) Feature  
— Asynchronous random access times of 45/45/55 ns  
(at 30 pF)  
Power dissipation (typical values, CL = 30 pF)  
— Burst Mode Read: 10 mA @ 80Mhz  
— Simultaneous Operation: 25 mA @ 80Mhz  
— Program/Erase: 15 mA  
— Device generates data output voltages and tolerates  
data input voltages as determined by the voltage on  
the VIO pin  
„
— 1.8V compatible I/O signals (1.65-1.95 V)  
— 1.5V compatible I/O signals (1.35-1.70 V)  
„
„
Simultaneous Read/Write operation  
— Standby mode: 0.2 µA  
— Data can be continuously read from one bank while  
executing erase/program functions in other bank  
— Zero latency between read and write operations  
— Four bank architecture: WS128J: 16Mb/48Mb/48Mb/  
16Mb, WS064J: 8Mb/24Mb/24Mb/8Mb  
Hardware Features  
„
„
„
Handshaking feature available  
— Provides host system with minimum possible latency  
by monitoring RDY  
Programable Burst Interface  
Hardware reset input (RESET#)  
— Hardware method to reset the device for reading  
array data  
— 2 Modes of Burst Read Operation  
— Linear Burst: 8, 16, and 32 words with wrap-around  
— Continuous Sequential Burst  
WP# input  
„
„
SecSi™ (Secured Silicon) Sector region  
— 128 words accessible through a command sequence,  
64words for the Factory SecSi™ Sector and 64words  
for the Customer SecSi™ Sector.  
Sector Architecture  
4 Kword x 16 boot sectors, eight at the top of the address  
range, and eight at the bottom of the address range  
— Write protect (WP#) function allows protection of  
four outermost boot sectors, regardless of sector  
protect status  
„
Persistent Sector Protection  
— A command sector protection method to lock  
combinations of individual sectors and sector groups  
to prevent program or erase operations within that  
sector  
WS128J: 4 Kword X 16, 32 Kword x 254 sectors  
Bank A : 4 Kword x 8, 32 Kword x 31 sectors  
— Sectors can be locked and unlocked in-system at VCC  
level  
Bank B : 32 Kword x 96 sectors  
Bank C : 32 Kword x 96 sectors  
„
„
Password Sector Protection  
— A sophisticated sector protection method to lock  
combinations of individual sectors and sector groups  
to prevent program or erase operations within that  
sector using a user-defined 64-bit password  
Bank D : 4 Kword x 8, 32 Kword x 31 sectors  
WS064J: 4 Kword x 16, 32 Kword x 126 sectors.  
Bank A : 4 Kword x 8, 32 Kword x 15 sectors  
Bank B : 32 Kword x 48 sectors  
ACC input: Acceleration function reduces  
programming time; all sectors locked when ACC =  
VIL  
Bank C : 32 Kword x 48 sectors  
Bank D : 4 Kword x 8, 32 Kword x 15 sectors  
„
„
CMOS compatible inputs, CMOS compatible outputs  
Low VCC write inhibit  
„
„
„
WS128J : 84-ball (8 mm x 11.6 mm) FBGA package,  
WS064J : 80-ball (7 mm x 9 mm) FBGA package  
Cyclling Endurance : 1,000,000 cycles per sector  
typical  
Data retention : 20-years typical  
Publication Number WS128J/064J_00 Revision A Amendment 1 Issue Date October 6, 2004  
This document contains information on a product under development at Spansion, LLC. The information is intended to help you evaluate this product. Do not design in  
this product without contacting the factory. Spansion reserves the right to change or discontinue work on this proposed product without notice.  

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