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S29PL127J70BAI001

更新时间： 2024-11-08 15:50:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
101页 7830K
描述
Flash, 8MX16, 70ns, PBGA80, FBGA-80

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S29PL127J70BAI001 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：VFBGA, BGA80,8X12,32Reach Compliance Code：compliant
ECCN代码：3A991.B.1.AHTS代码：8542.32.00.51
风险等级：5.21最长访问时间：70 ns
其他特性：TOP AND BOTTOM BOOT BLOCK启动块：BOTTOM/TOP
命令用户界面：YES通用闪存接口：YES
数据轮询：YESJESD-30 代码：R-PBGA-B80
长度：11 mm内存密度：134217728 bit
内存集成电路类型：FLASH内存宽度：16
功能数量：1部门数/规模：16,254
端子数量：80字数：8388608 words
字数代码：8000000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：8MX16封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装等效代码：BGA80,8X12,32
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
页面大小：8 words并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3/3.3 V
编程电压：3 V认证状态：Not Qualified
就绪/忙碌：YES座面最大高度：1 mm
部门规模：4K,32K最大待机电流：0.000005 A
子类别：Flash Memories最大压摆率：0.07 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
切换位：YES类型：NOR TYPE
宽度：8 mmBase Number Matches：1

S29PL127J70BAI001 数据手册

 浏览型号S29PL127J70BAI001的Datasheet PDF文件第2页浏览型号S29PL127J70BAI001的Datasheet PDF文件第3页浏览型号S29PL127J70BAI001的Datasheet PDF文件第4页浏览型号S29PL127J70BAI001的Datasheet PDF文件第5页浏览型号S29PL127J70BAI001的Datasheet PDF文件第6页浏览型号S29PL127J70BAI001的Datasheet PDF文件第7页 
S29PL-J  
128-/128-/64-/32-Mbit (8/8/4/2M x 16-Bit)  
3V, Flash with Enhanced VersatileIO™  
Distinctive Characteristics  
– Output voltage generated and input voltages tolerated on  
all control inputs and I/Os is determined by the voltage on  
the VIO pin  
– VIO options at 1.8 V and 3 V I/O for PL127J and PL129J  
devices  
Architectural Advantages  
128-/128-/64-/32-Mbit Page Mode devices  
– Page size of 8 words: Fast page read access from random  
locations within the page  
Single power supply operation  
– 3V VIO for PL064J and PL032J devices  
Secured Silicon Sector region  
– Full Voltage range: 2.7 to 3.6 V read, erase, and program  
operations for battery-powered applications  
Dual Chip Enable inputs (only in PL129J)  
– Two CE# inputs control selection of each half of the  
memory space  
Simultaneous Read/Write Operation  
– Data can be continuously read from one bank while  
executing erase/program functions in another bank  
– Zero latency switching from write to read operations  
FlexBank Architecture (PL127J/PL064J/PL032J)  
– 4 separate banks, with up to two simultaneous operations  
per device  
– Up to 128 words accessible through a command sequence  
– Up to 64 factory-locked words  
– Up to 64 customer-lockable words  
Both top and bottom boot blocks in one device  
Manufactured on 110-nm process technology  
Data Retention: 20 years typical  
Cycling Endurance: 1 million cycles per sector typical  
Performance Characteristics  
High Performance  
– Page access times as fast as 20 ns  
– Random access times as fast as 55 ns  
Power consumption (typical values at 10 MHz)  
– 45 mA active read current  
– Bank A:  
PL127J -16 Mbit (4 Kw 8 and 32 Kw 31)  
PL064J - 8 Mbit (4 Kw 8 and 32 Kw 15)  
PL032J - 4 Mbit (4 Kw 8 and 32 Kw 7)  
– Bank B:  
– 17 mA program/erase current  
– 0.2 A typical standby mode current  
PL127J - 48 Mbit (32 Kw 96)  
PL064J - 24 Mbit (32 Kw 48)  
PL032J - 12 Mbit (32 Kw 24)  
Software Features  
Software command-set compatible with JEDEC 42.4  
standard  
– Bank C:  
PL127J - 48 Mbit (32 Kw 96)  
PL064J - 24 Mbit (32 Kw 48)  
PL032J - 12 Mbit (32 Kw 24)  
– Backward compatible with Am29F, Am29LV, Am29DL, and  
AM29PDL families and MBM29QM/RM, MBM29LV,  
MBM29DL, MBM29PDL families  
– Bank D:  
CFI (Common Flash Interface) compliant  
– Provides device-specific information to the system,  
allowing host software to easily reconfigure for different  
Flash devices  
PL127J -16 Mbit (4 Kw 8 and 32 Kw 31)  
PL064J - 8 Mbit (4 Kw 8 and 32 Kw 15)  
PL032J - 4 Mbit (4 Kw 8 and 32 Kw 7)  
FlexBank Architecture (PL129J)  
– 4 separate banks, with up to two simultaneous operations  
per device  
Erase Suspend / Erase Resume  
– Suspends an erase operation to allow read or program  
operations in other sectors of same bank  
Program Suspend / Program Resume  
– Suspends a program operation to allow read operation  
from sectors other than the one being programmed  
Unlock Bypass Program command  
– CE#1 controlled banks:  
Bank 1A: PL129J - 16-Mbit (4Kw 8 and 32Kw 31)  
Bank 1B: PL129J - 48-Mbit (32Kw 96)  
– CE#2 controlled banks:  
Bank 2A: PL129J - 48-Mbit (32 Kw 96)  
Bank 2B: PL129J - 16-Mbit (4 Kw 8 and 32 Kw 31)  
Enhanced VersatileI/O (VIO) Control  
Reduces overall programming time when issuing multiple  
program command sequences  
Cypress Semiconductor Corporation  
Document Number: 002-00615 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 10, 2016  
1234567...101

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