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S29JL032H90TAI2233 PDF预览

S29JL032H90TAI2233

更新时间： 2024-11-05 15:50:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 内存集成电路
页数 文件大小 规格书
58页 2180K
描述
Flash

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中文翻译

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S29JL032H90TAI2233 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：compliant风险等级：5.74
内存集成电路类型：FLASH峰值回流温度（摄氏度）：NOT SPECIFIED
编程电压：3 V处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

S29JL032H90TAI2233 数据手册

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S29JL032H  
32 Mbit (4 M x 8-Bit/2 M x 16-Bit), 3 V  
Simultaneous Read/Write Flash  
Distinctive Characteristics  
– 200 nA in standby or automatic slp mode  
Architectural Advantages  
Cycling Endurance: 1 million cycles per sector typical  
Simultaneous Read/Write Operations  
Data Retention: 20 years typical  
– Data can be continuously read from one bank while executing  
erase/program functions in another bank.  
Software Features  
– Zero latency between read and write operations  
Multiple Bank Architecture  
Supports Common Flash Memory Inerface (CFI)  
– Four bank architectures available (refer to Table on page 11).  
Boot Sectors  
Erase SuspendErse Resume  
– Suspends erase operations to read data from, or program data to,  
a sectot is not being ersed, then resumes the erase  
operaion.  
– Top and bottom boot sectors in the same device  
– Any combination of sectors can be erased  
Manufactured on 0.13 µm Process Technology  
Data# Polling and Togge Bits  
Provides a software method of detecting the status of program or  
erase cycles  
Secured Silicon Sector: Extra 256 Byte sector  
– Customer lockable: One-time programmable only. Once locked,  
data cannot be changed  
Unlock BypProgram Command  
– Reduces overall programming time when issuing multiple  
program command sequences  
Zero Power Operation  
– Sophisticated power management circuits reduce power  
consumed during inactive periods to nearly zero.  
Hardware Features  
Compatible with JEDEC standards  
– Pinout and software compatible with single-power-supply flash  
standard  
eady/Busy# Output (RY/BY#)  
– Hardware method for detecting program or erase cycle  
completion  
Hardware Reset Pin (RESET#)  
– Hardware method of resetting the internal state machine to the  
read mode  
Package options  
48-pin TSOP  
WP#/ACC Input Pin  
Performance Characteristics  
– Write protect (WP#) function protects the two outermost boot  
sectors regardless of sector protect status  
High Performance  
– Access time as fast as 60
– Acceleration (ACC) function accelerates program timing  
– Program time: 4 µs/word tycal using accelerated programming  
function  
Sector Protection  
– Hardware method to prevent any program or erase operation  
within a sector  
Ultra Low Power Consumption (typicvalues)  
– 2 mA active read current at 1 MHz  
– Temporary Sector Unprotect allows changing data in protected  
sectors in-system  
– 10 mA active read current at 5 MHz  
General Descripion  
The S29JL032H is a 2 megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304  
bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed to  
be programmed system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers.  
The device is available with an access time of 60, 70, or 90 ns and is offered in a 48-pin TSOP package. Standard control pins—  
chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus  
contention issues.  
The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated  
voltages are provided for the program and erase operations.  
Cypress Semiconductor Corporation  
Document Number: 002-01186 Rev. *A  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised December 08, 2015  
1234567...58

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