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S29CD016J0PQAI123 PDF预览

S29CD016J0PQAI123

更新时间: 2024-10-29 08:10:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
74页 1356K
描述
Flash, 512KX32, 54ns, PQFP80, QFP-80

S29CD016J0PQAI123 数据手册

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S29CD032J  
S29CD016J  
S29CL032J  
S29CL016J  
Contents  
1.  
Ordering Information................................................... 4  
9.2 Secured Silicon Sector Entry  
and Exit Commands...................................................... 45  
1.1 Valid Combinations........................................................ 5  
10. Electronic Marking...................................................... 46  
2.  
Input/Output Descriptions  
and Logic Symbols...................................................... 6  
11. Power Conservation Modes....................................... 46  
11.1 Standby Mode............................................................... 46  
11.2 Automatic Sleep Mode.................................................. 46  
11.3 Hardware RESET# Input Operation.............................. 46  
11.4 Output Disable (OE#).................................................... 46  
3.  
4.  
Block Diagram.............................................................. 7  
Block Diagram of Simultaneous  
Read/Write Circuit........................................................ 8  
5.  
Physical Dimensions/Connection Diagrams............. 9  
12. Electrical Specifications............................................. 47  
12.1 Absolute Maximum Ratings.......................................... 47  
5.1 80-Pin PQFP Connection Diagram................................ 9  
5.2 PQR080–80-Lead Plastic Quad Flat  
Package Physical Dimensions..................................... 10  
5.3 80-Ball Fortified BGA Connection Diagram ................. 11  
5.4 Special Package Handling Instructions........................ 11  
5.5 LAA080–80-ball Fortified Ball Grid Array  
13. Operating Ranges....................................................... 48  
14. DC Characteristics...................................................... 49  
14.1 Zero Power Flash.......................................................... 50  
(13 x 11 mm) Physical Dimensions.............................. 12  
5.6 LAD080–80-ball Fortified Ball Grid Array  
15. Test Conditions........................................................... 51  
16. Test Specifications ..................................................... 51  
16.1 Switching Waveforms ................................................... 51  
(11 x 9 mm) Physical Dimensions................................ 13  
6.  
6.1 Memory Map................................................................ 14  
7. Device Operations ..................................................... 19  
7.1 Device Operation Table ............................................... 19  
7.2 Asynchronous Read..................................................... 20  
7.3 Hardware Reset (RESET#).......................................... 21  
7.4 Synchronous (Burst) Read Mode  
and Configuration Register .......................................... 21  
7.5 Autoselect .................................................................... 26  
7.6 VersatileI/O (VIO) Control............................................. 27  
7.7 Program/Erase Operations .......................................... 27  
7.8 Write Operation Status................................................. 32  
7.9 Reset Command.......................................................... 36  
Product Overview ...................................................... 14  
17. AC Characteristics...................................................... 52  
17.1 VCC and VIO Power-up.................................................. 52  
17.2 Asynchronous Operations............................................. 52  
17.3 Synchronous Operations .............................................. 54  
17.4 Hardware Reset (RESET#)........................................... 56  
17.5 Write Protect (WP#)...................................................... 57  
17.6 Erase/Program Operations........................................... 57  
17.7 Alternate CE# Controlled  
Erase/Program Operations........................................... 62  
17.8 Erase and Programming Performance ......................... 63  
17.9 PQFP and Fortified BGA Pin Capacitance ................... 63  
18. Appendix 1 .................................................................. 64  
18.1 Common Flash Memory Interface (CFI) ....................... 64  
8.  
Advanced Sector Protection/Unprotection ............. 37  
19. Appendix 2 .................................................................. 67  
19.1 Command Definitions.................................................... 67  
8.1 Advanced Sector Protection Overview ........................ 38  
8.2 Persistent Protection Bits............................................. 39  
8.3 Persistent Protection Bit Lock Bit................................. 41  
8.4 Dynamic Protection Bits............................................... 41  
8.5 Password Protection Method....................................... 42  
8.6 Hardware Data Protection Methods............................. 43  
20. Revision History.......................................................... 69  
Sales, Solutions, and Legal Information .......................... 74  
Worldwide Sales and Design Support ........................... 74  
Products ........................................................................ 74  
PSoC® Solutions .......................................................... 74  
Cypress Developer Community ..................................... 74  
Technical Support ......................................................... 74  
9.  
Secured Silicon Sector Flash Memory Region ....... 44  
9.1 Secured Silicon Sector Protection Bit .......................... 45  
Document Number: 002-00948 Rev. *C  
Page 3 of 74  

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