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S25FL256SAGMFVG00 PDF预览

S25FL256SAGMFVG00

更新时间: 2024-11-08 18:20:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管内存集成电路
页数 文件大小 规格书
149页 4581K
描述
Flash, 32MX8, PDSO16, SOIC-16

S25FL256SAGMFVG00 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP, SOP16,.4Reach Compliance Code:compliant
HTS代码:8542.32.00.51风险等级:2.09
其他特性:ALSO CONFIGURABLE AS 256M X 1备用内存宽度:2
最大时钟频率 (fCLK):133 MHz数据保留时间-最小值:20
耐久性:100000 Write/Erase CyclesJESD-30 代码:R-PDSO-G16
长度:10.3 mm内存密度:268435456 bit
内存集成电路类型:FLASH内存宽度:8
功能数量:1端子数量:16
字数:33554432 words字数代码:32000000
工作模式:SYNCHRONOUS最高工作温度:105 °C
最低工作温度:-40 °C组织:32MX8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:SERIAL
电源:3/3.3 V编程电压:3 V
认证状态:Not Qualified座面最大高度:2.65 mm
串行总线类型:SPI最大待机电流:0.0003 A
子类别:Flash Memories最大压摆率:0.1 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL类型:NOR TYPE
宽度:7.5 mm最长写入周期时间 (tWC):500 ms
写保护:HARDWARE/SOFTWAREBase Number Matches:1

S25FL256SAGMFVG00 数据手册

 浏览型号S25FL256SAGMFVG00的Datasheet PDF文件第2页浏览型号S25FL256SAGMFVG00的Datasheet PDF文件第3页浏览型号S25FL256SAGMFVG00的Datasheet PDF文件第4页浏览型号S25FL256SAGMFVG00的Datasheet PDF文件第5页浏览型号S25FL256SAGMFVG00的Datasheet PDF文件第6页浏览型号S25FL256SAGMFVG00的Datasheet PDF文件第7页 
S25FL128S/S25FL256S  
128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte)  
3.0V SPI Flash Memory  
Features  
CMOS 3.0 Volt Core with Versatile I/O  
Serial Peripheral Interface (SPI) with Multi-I/O  
– SPI Clock polarity and phase modes 0 and 3  
– Double Data Rate (DDR) option  
Cycling Endurance  
– 100,000 Program-Erase Cycles, minimum  
Data Retention  
– 20 Year Data Retention, minimum  
– Extended Addressing: 24- or 32-bit address options  
– Serial Command set and footprint compatible with  
S25FL-A, S25FL-K, and S25FL-P SPI families  
– Multi I/O Command set and footprint compatible with  
S25FL-P SPI family  
Security features  
– One Time Program (OTP) array of 1024 bytes  
– Block Protection:  
– Status Register bits to control protection against  
program or erase of a contiguous range of sectors.  
– Hardware and software control options  
– Advanced Sector Protection (ASP)  
– Individual sector protection controlled by boot code or  
password  
READ Commands  
– Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad  
DDR  
– AutoBoot - power up or reset and execute a Normal or  
Quad read command automatically at a preselected  
address  
– Common Flash Interface (CFI) data for configuration  
information.  
Cypress® 65 nm MirrorBit® Technology with Eclipse™  
Architecture  
Core Supply Voltage: 2.7V to 3.6V  
I/O Supply Voltage: 1.65V to 3.6V  
– SO16 and FBGA packages  
Programming (1.5 Mbytes/s)  
– 256 or 512 Byte Page Programming buffer options  
– Quad-Input Page Programming (QPP) for slow clock  
systems  
– Automatic ECC -internal hardware Error Correction Code  
generation with single bit error correction  
Temperature Range / Grade:  
– Industrial (-40°C to +85°C)  
– Industrial Plus (-40°C to +105°C)  
– Automotive AEC-Q100 Grade 3 (-40°C to +85°C)  
– Automotive AEC-Q100 Grade 2 (-40°C to +105°C)  
– Automotive AEC-Q100 Grade 1 (-40°C to +125°C)  
Erase (0.5 to 0.65 Mbytes/s)  
– Hybrid sector size option - physical set of thirty two 4-kbyte  
sectors at top or bottom of address space with all  
remaining sectors of 64 kbytes, for compatibility with prior  
generation S25FL devices  
Packages (all Pb-free)  
– 16-lead SOIC (300 mil)  
– WSON 6 x 8 mm  
– BGA-24 6 x 8 mm  
– Uniform sector option - always erase 256-kbyte blocks for  
software compatibility with higher density and future  
devices.  
– 5 x 5 ball (FAB024) and 4 x 6 ball (FAC024) footprint  
options  
Cypress Semiconductor Corporation  
Document Number: 001-98283 Rev. *N  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 14, 2017  

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