S25FL128S/S25FL256S
128 Mb (16 MB)/256 Mb (32 MB)
3.0V SPI Flash Memory
Features
■ CMOS 3.0 Volt Core with Versatile I/O
■ Data Retention
❐ 20 Year Data Retention, minimum
■ SPI with Multi-I/O
■ Security features
❐ OTP array of 1024 bytes
❐ SPI Clock polarity and phase modes 0 and 3
❐ DDR option
❐ Extended Addressing: 24- or 32-bit address options
❐ Block Protection:
❐ Serial Command set and footprint compatible with
S25FL-A, S25FL-K, and S25FL-P SPI families
• Status Register bits to control protection against program
or erase of a contiguous range of sectors.
❐ Multi I/O Command set and footprint compatible with
• Hardware and software control options
S25FL-P SPI family
❐ Advanced Sector Protection (ASP)
• Individual sector protection controlled by boot code or
password
■ READ Commands
❐ Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
❐ AutoBoot - power up or reset and execute a Normal or Quad
■ Cypress® 65 nm MirrorBit® Technology with Eclipse™
Architecture
read command automatically at a preselected address
❐ Common Flash Interface (CFI) data for configuration infor-
mation.
■ Core Supply Voltage: 2.7V to 3.6V
■ Programming (1.5 MBps)
❐ 256 or 512 Byte Page Programming buffer options
❐ Quad-Input Page Programming (QPP) for slow clock sys-
tems
❐ Automatic ECC-internal hardware Error Correction Code
generation with single bit error correction
■ I/O Supply Voltage: 1.65V to 3.6V
❐ SO16 and FBGA packages
■ Temperature Range / Grade:
❐ Industrial (40°C to +85°C)
❐ Industrial Plus (40°C to +105°C)
❐ Automotive AEC-Q100 Grade 3 (40°C to +85°C)
❐ Automotive AEC-Q100 Grade 2 (40°C to +105°C)
❐ Automotive AEC-Q100 Grade 1 (40°C to +125°C)
■ Erase (0.5 to 0.65 MBps)
❐ Hybrid sector size option - physical set of thirty two 4-KB
sectors at top or bottom of address space with all remaining
sectors of 64 KB, for compatibility with prior generation S25-
FL devices
❐ Uniform sector option - always erase 256-KB blocks for soft-
ware compatibility with higher density and future devices.
■ Packages (all Pb-free)
❐ 16-lead SOIC (300 mil)
❐ WSON 6 8 mm
❐ BGA-24 6 8 mm
• 5 5 ball (FAB024) and 4 6 ball (FAC024) footprint
options
■ Cycling Endurance
❐ 100,000 Program-Erase Cycles, minimum
• Known Good Die (KGD) and Known Tested Die
Logic Block Diagram
CS#
SRAM
SCK
MirrorBit Array
SI/IO0
SO/IO1
WP#/IO2
Y Decoders
Data Latch
I/O
Control
Logic
HOLD#/IO3
Data Path
RESET#
Cypress Semiconductor Corporation
Document Number: 001-98283 Rev. *Q
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 30, 2019