Datasheet > S2202TB

S2202TB

更新时间： 2024-02-04 14:19:44

品牌	Logo	应用领域
AMCC		以太网：16GBASE-T 电信电信集成电路
页数	文件大小	规格书
8页	111K
描述
Ethernet Transceiver, PBGA156, 21 X 21 MM, COMPACT, TBGA-156

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S2202TB 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LBGA,
针数：	156	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.86
JESD-30 代码：	S-PBGA-B156	长度：	21 mm
功能数量：	1	端子数量：	156
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	1.65 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ETHERNET TRANSCEIVER
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	21 mm
Base Number Matches：	1

S2202TB 数据手册

Revision 1.0 - February 25, 2000

APPLICATION NOTE

S2202 Application Note and Reference

Diagrams

When laying out a high-speed part, the high-speed I/O should be considered first. The differential receive pairs are

Ω

shown with 100 line-to-line termination resistors. The resistors should be placed as close to the receive inputs as

possible while adhering to layout rules. The differential transmit pairs are shown with pull-down resistors. If pull-

down resistors are included they should be placed as close as possible to the transmit outputs while adhering to

layout rules. AC coupling capacitors are not shown in this layout. They are typically included in the high-speed sig-

nal path in order to insure that the DC bias of the high-speed PECL outputs does not affect the inputs. There is no

requirement to place the coupling capacitors close to either the transmitting or receiving part. If a signal is routed

through a connector, the AC coupling capacitors are often laid out close to the connector. If AC coupling capacitors

are employed, they may be included with the outputs, the inputs, or both places¹. When two parts from the AMCC

SiliconHiway™ family are connected, coupling capacitors are not required to reconcile DC levels. However, there

are several design considerations that may make it desirable to include them. In applications where a board may

be hot swapped, it is likely that the high speed I/O will be excited before the chip has been powered up. Adding

coupling capacitors insures that the signal on any input (or output) will not be more than approximately one volt.

At gigabit rates, the high-speed traces exhibit transmission line effects. It is important to keep the trace lengths of

differential pairs the same length in order to minimize skew, and to use either chamfered or rounded corners in

order to reduce ElectroMagnetic Interference (EMI) and impedance mismatches. In Figure 6, the high-speed lines

are microstrip traces (placed on the surface of the board above a power or ground plane). These can also be laid

out as stripline traces (sandwiched between power/ground planes on an internal signal plane) by including vias

close to the termination/pull-down resistors. Stripline traces have the advantage of better EMI shielding, but the

vias cause small impedance mismatches that will result in small reflections in the signal lines.

Following the high-speed I/O traces, the reference clock input, loop filter, and analog power decoupling are the

most important layout features. Each of these is critical because they could potentially offer a path for noise into the

analog portion of the chip, which translates into jitter. The clock line should be kept as short as possible, and care

should be taken to minimize the potential for crosstalk or noise coupling onto the clock line. The loop filter is shown

Ω

in the upper left corner of Figure 6. Two 270 resistors are connected to the external loop filter pins, with an AC

coupling capacitor (22 nF) between them. The entire loop filter is surrounded by a ground ring to increase noise

immunity. The analog power pins are connected to a power planelet, which should be created on one of the signal

planes. The planelet is isolated from the power plane by a ferrite (see Table 1). Close to the ferrite, the power plane

is decoupled to ground by a large capacitor (10 F). In addition, decoupling capacitors are added close to each

analog power pin.

Finally, decoupling capacitors are added around the chip as space allows. Due to the ball density of BGA pack-

ages, it is not reasonable to attempt to decouple every power pin. Where space permits, power pins are directly

decoupled. In addition, capacitors are sprinkled around the chip, the most notable of which is the 10 F capacitor in

the center of the chip. Note that multiple vias are employed to both the power and ground planes to reduce the

impedance between the capacitor pads and the respective planes.

Applications where hot swapping of boards is required often employ AC coupling capacitors at both the input and the output to insure that DC

levels do not harm the chip prior to power on.

1...4 5 678

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