Datasheet > S2204TB

S2204TB

更新时间： 2024-02-17 08:17:39

品牌	Logo	应用领域
AMCC		以太网：16GBASE-T 电信电信集成电路
页数	文件大小	规格书
33页	339K
描述
Ethernet Transceiver, 4-Trnsvr, CMOS, PBGA208, 23 X 23 MM, COMPACT, TBGA-208

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中文翻译

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技术参数
数据手册

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S2204TB 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LBGA, BGA208,17X17,50
针数：	208	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.87
数据速率：	1000000 Mbps	JESD-30 代码：	S-PBGA-B208
长度：	23 mm	功能数量：	1
端子数量：	208	收发器数量：	4
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA208,17X17,50	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.65 mm	子类别：	Network Interfaces
最大压摆率：	980 mA	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	ETHERNET TRANSCEIVER	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	23 mm	Base Number Matches：	1

S2204TB 数据手册

DEVICE

SPECIFICATION

QUAD GIGABIT ETHERNET DEVICE

S2204

QUAD GIGABIT ETHERNET DEVICE

FEATURES

GENERAL DESCRIPTION

• 1250 MHz (Gigabit Ethernet) operating rate

- 1/2 Rate Operation

The S2204 facilitates high-speed serial transmission

of data in a variety of applications including Gigabit

Ethernet, serial backplanes, and proprietary point to

point links. The chip provides four separate trans-

ceivers which can be operated individually for a data

capacity of >4 Gbps.

• IEEE 802.3z Gigabit Ethernet Compatible

• Quad Transmitter with phase-locked loop (PLL)

clock synthesis from low speed reference

• Quad Receiver PLL provides clock and data

recovery

Each bi-directional channel provides parallel to serial

and serial to parallel conversion, clock generation/

recovery, and framing. The on-chip transmit PLL

synthesizes the high-speed clock from a low-speed

reference. The on-chip quad receive PLL is used for

clock recovery and data re-timing on the four inde-

pendent data inputs. The transmitter and receiver

each support differential PECL-compatible I/O for

copper or fiber optic component interfaces with ex-

cellent signal integrity. Local loopback mode allows

for system diagnostics. The chip requires a 3.3V

power supply and dissipates 2.5 watts.

• Internally series terminated TTL outputs

• Low-jitter serial PECL interface

• Individual local loopback control

• JTAG 1149.1 Boundary scan on low speed I/O

signals

• Interfaces with coax, twinax, or fiber optics

• Single +3.3V supply, 2.5 W power dissipation

• Compact 23mm x 23mm 208 TBGA package

APPLICATIONS

Figure 1 shows the S2204 and S2004 in a Gigabit

Ethernet application. Figure 2 combines the

S2204 with a crosspoint switch to demonstrate a

serial backplane application. Figure 3 is the input/

output diagram. Figures 4 and 5 show the transmit

and receive block diagrams, respectively.

• Ethernet Backbones

• Workstation

• Frame buffer

• Switched networks

• Data broadcast environments

• Proprietary extended backplanes

Figure 1. Typical Quad Gigabit Ethernet Application

GE INTERFACE

SERIAL BP DRIVER

MAC

(ASIC)

MAC

(ASIC)

TO SERIAL BACKPLANE

QUAD

GIGABIT

ETHERNET

S2204

S2004

MAC

(ASIC)

INTERFACE

MAC

(ASIC)

October 9, 2000 / Revision E

12 3 4 5 6 7...33

中文翻译

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