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RTSX72SU-CQ208EV PDF预览

RTSX72SU-CQ208EV

更新时间: 2024-11-24 15:50:03
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟可编程逻辑
页数 文件大小 规格书
100页 5065K
描述
Field Programmable Gate Array, 6036 CLBs, 108000 Gates, 310MHz, 6036-Cell, CMOS, CQFP208, CERAMIC, QFP-208

RTSX72SU-CQ208EV 技术参数

生命周期:Active零件包装代码:QFP
包装说明:CERAMIC, QFP-208针数:208
Reach Compliance Code:compliantECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01风险等级:5.79
其他特性:72000 TYPICAL GATES AVAILABLE最大时钟频率:310 MHz
CLB-Max的组合延迟:1.4 nsJESD-30 代码:S-CQFP-F208
长度:29.21 mm可配置逻辑块数量:6036
等效关口数量:108000输入次数:170
逻辑单元数量:6036输出次数:170
端子数量:208最高工作温度:125 °C
最低工作温度:-55 °C组织:6036 CLBS, 108000 GATES
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:HGQFF
封装等效代码:TPAK208,2.9SQ,20封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, GUARD RING电源:2.5,3.3/5 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
筛选级别:MIL-PRF-38535 Class V座面最大高度:3.3 mm
子类别:Field Programmable Gate Arrays最大供电电压:2.75 V
最小供电电压:2.25 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子节距:0.5 mm端子位置:QUAD
总剂量:100k Rad(Si) V宽度:29.21 mm
Base Number Matches:1

RTSX72SU-CQ208EV 数据手册

 浏览型号RTSX72SU-CQ208EV的Datasheet PDF文件第2页浏览型号RTSX72SU-CQ208EV的Datasheet PDF文件第3页浏览型号RTSX72SU-CQ208EV的Datasheet PDF文件第4页浏览型号RTSX72SU-CQ208EV的Datasheet PDF文件第5页浏览型号RTSX72SU-CQ208EV的Datasheet PDF文件第6页浏览型号RTSX72SU-CQ208EV的Datasheet PDF文件第7页 
Revision 8  
RTSX-SU Radiation-Tolerant FPGAs (UMC)  
Designed for Space  
Specifications  
SEU-Hardened Registers Eliminate the Need to Implement  
Triple-Module Redundancy (TMR)  
0.25 µm Metal-to-Metal Antifuse Process (UMC)  
48,000 to 108,000 Available System Gates  
Up to 2,012 SEU-Hardened Flip-Flops  
– Immune to Single Event Upsets (SEU) to LET > 40 MeV-  
th  
2
cm /mg,  
Up to 360 User-Programmable I/O Pins  
–10  
– SEU Rate  
<
10  
Upset/Bit-Day in Worst-Case  
Geosynchronous Orbit  
Up to 100 krad (Si) Total Ionizing Dose (TID)  
Features  
Very Low Power Consumption (Up to 68 mW at Standby)  
3.3 V and 5 V Mixed Voltage  
Configurable I/O Support for 3.3 V/5 V PCI, LVTTL, TTL, and  
CMOS  
– Parametric Performance Supported with Lot-Specific Test  
Data  
Single-Event Latch-Up (SEL) Immunity to LET > 104  
TH  
MeVcm2/mg  
TM1019.5 Test Data Available  
QML Certified Devices  
– 5 V Input Tolerance and 5 V Drive Strength  
– Slow Slew Rate Option  
– Configurable Weak Resistor Pull-Up/Down for Tristated  
Outputs at Power-Up  
High Performance  
– Hot-Swap Compliant with Cold-Sparing Support  
Secure Programming Technology Designed to Protect Against  
Reverse Engineering and Design Theft  
100% Circuit Resource Utilization with 100% Pin Locking  
Unique In-System Diagnostic and Verification Capability with  
Silicon Explorer II  
Deterministic, User-Controllable Timing  
JTAG Boundary Scan Testing in Compliance with IEEE  
Standard 1149.1 – Dedicated JTAG Reset (TRST) Pin  
230 MHz System Performance  
310 MHz Internal Performance  
9.5 ns Input Clock to Output Pad  
Processing Flows  
B-Flow – MIL-STD-883B  
E-Flow – Extended Flow  
EV-Flow – Class V Equivalent Flow Processing Consistent with  
MIL-PRF 38535  
Prototyping Options  
Commercial SX-A Devices for Functional Verification  
RTSX-SU PROTO Devices with Same Functional and Timing  
Characteristics as Flight Unit in a Non-Hermetic Package  
Table 1 • RTSX-SU Product Profile  
Device  
RTSX32SU  
RTSX72SU  
Capacity  
Typical Gates  
System Gates  
32,000  
48,000  
72,000  
108,000  
Logic Modules  
Combinatorial Cells  
SEU-Hardened Register Cells (Dedicated Flip-Flops)  
2,880  
1,800  
1,080  
6,036  
4,024  
2,012  
Maximum Flip-Flops  
Maximum User I/Os  
Clocks  
1,980  
227  
3
4,024  
360  
3
Quadrant Clocks  
Speed Grades  
0
4
Std., –1  
Std., –1  
Package (by pin count)  
CQ  
CG  
CC  
84, 208, 256  
256  
208, 256  
624  
January 2012  
i
© 2012 Microsemi Corporation  

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