Datasheet > RT54SX72S

RT54SX72S

更新时间： 2024-09-25 06:08:51

品牌	Logo	应用领域
ACTEL		/
页数	文件大小	规格书
84页	658K
描述
RTSX-S RadTolerant FPGAs

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中文翻译

获取价格

数据手册

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RT54SX72S 数据手册

v2.2

™

RTSX-S RadTolerant FPGAs

Designed for Space

Features

•

SEU-Hardened Registers Eliminate the Need to

Implement Triple-Module Redundancy (TMR)

•

Very Low Power Consumption (Up to 68 mW at

Standby)

–

Immune to Single-Event Upsets (SEU) to LET_th

•

3.3V and 5V Mixed Voltage

Configurable I/O Support for 3.3V/5V PCI, LVTTL,

TTL, and CMOS

> 40 MeV-cm²/mg,

–

SEU Rate < 10^–10Upset/Bit-Day in Worst-Case

Geosynchronous Orbit

–

5V Input Tolerance and 5V Drive Strength

Slow Slew Rate Option

Configurable Weak Resistor Pull-Up/Down for

Tristated Outputs at Power-Up

•

Up to 100 krad (Si) Total Ionizing Dose (TID)

–

Parametric Performance Supported with Lot-

Specific Test Data

–

Hot-Swap

Support

Compliant

with

Cold-Sparing

•

Single-Event Latch-Up (SEL) Immunity

TM1019.5 Test Data Available

QML Certified Devices

•

Secure Programming Technology Prevents Reverse

Engineering and Design Theft

100% Circuit Resource Utilization with 100% Pin

Locking

Unique In-System Diagnostic and Verification

Capability with Silicon Explorer II

Low-Cost Prototyping Option

Deterministic, User-Controllable Timing

JTAG Boundary Scan Testing in Compliance with

IEEE Standard 1149.1 – Dedicated JTAG Reset

(TRST) Pin

High Performance

•

230 MHz System Performance

310 MHz Internal Performance

9.5 ns Input Clock to Output Pad

•

Specifications

•

0.25 µm Metal-to-Metal Antifuse Process

48,000 to 108,000 Available System Gates

Up to 2,012 SEU-Hardened Flip-Flops

Up to 360 User-Programmable I/O Pins

Table 1 • RTSX-S Product Profile

Device

RT54SX32S

RT54SX72S

Capacity

Typical Gates

System Gates

32,000

48,000

72,000

108,000

Logic Modules

2,880

1,800

1,080

6,036

4,024

2,012

Combinatorial Cells

SEU-Hardened Register Cells (Dedicated Flip-Flops)

Maximum Flip-Flops

Maximum User I/Os

Clocks

1,980

227

4,024

360

Quadrant Clocks

Speed Grades

Std., –1

Package (by pin count)

CQFP

CCGA

CCLG

208, 256

256

208, 256

624

November 2004

See Actel’s website for the latest version of the datasheet

12 3 4 5 6 7...84

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RT54SX72S-1CG256M	ACTEL	获取价格	RTSX-S RadTolerant FPGAs
RT54SX72S-1CQ256B	ACTEL	获取价格	RTSX-S RadTolerant FPGAs
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