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RT14100A-STDCQ256M PDF预览

RT14100A-STDCQ256M

更新时间: 2024-11-02 09:30:55
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟可编程逻辑
页数 文件大小 规格书
54页 313K
描述
Field Programmable Gate Array, 85MHz, 1377-Cell, CMOS, CQFP256,

RT14100A-STDCQ256M 技术参数

生命周期:Obsolete包装说明:GQFF, TPAK256,3SQ,20
Reach Compliance Code:compliant风险等级:5.83
最大时钟频率:85 MHzJESD-30 代码:S-XQFP-F256
输入次数:228逻辑单元数量:1377
输出次数:228端子数量:256
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC封装代码:GQFF
封装等效代码:TPAK256,3SQ,20封装形状:SQUARE
封装形式:FLATPACK, GUARD RING电源:5 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
子类别:Field Programmable Gate Arrays标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子节距:0.5 mm端子位置:QUAD
Base Number Matches:1

RT14100A-STDCQ256M 数据手册

 浏览型号RT14100A-STDCQ256M的Datasheet PDF文件第2页浏览型号RT14100A-STDCQ256M的Datasheet PDF文件第3页浏览型号RT14100A-STDCQ256M的Datasheet PDF文件第4页浏览型号RT14100A-STDCQ256M的Datasheet PDF文件第5页浏览型号RT14100A-STDCQ256M的Datasheet PDF文件第6页浏览型号RT14100A-STDCQ256M的Datasheet PDF文件第7页 
v 3 . 1  
RadTolerant FPGAs  
Features  
Up to 60 MHz System Performance  
Up to 228 User I/Os  
Up to Four Fast, Low-Skew Clock Networks  
General Characteristics  
Tested Total Ionizing Dose (TID) Survivability Level  
No Single Event Latch-Up Below a Minimum LET  
(Linear Energy Transfer) Threshold of 80 MeV-cm2/mg  
for All RT (RadTolerant) Devices  
Easy Logic Integration  
Packages: 84-Pin, 132-Pin, 172-Pin, 196-Pin, and  
256-Pin Ceramic Quad Flat Pack  
Offered as Class B and E-Flow (Actel Space Level  
Flow)  
Nonvolatile, User Programmable  
Pin-Compatible Commercial Devices Available for  
Prototyping  
Highly Predictable Performance with 100%  
Automatic Place-and-Route  
100% Resource Utilization with 100% Pin-Locking  
Secure Programming Technology Prevents Reverse  
Engineering and Design Theft  
QML Certified Devices  
100% Military Temperature Tested (–55°C to  
+125°C)  
Permanently Programmed for Operation on  
Power-Up  
Unique In-System Diagnostic and Verification  
Capability with Silicon Explorer  
High Density and Performance  
4,000 to 20,000 Logic Equivalent Gates  
2,000 to 10,000 ASIC Equivalent Gates  
Up to 85 MHz Internal Performance  
Product Family Profile  
Table 1 •  
De vice  
RadTolerant Family  
RT1020  
RT1280A  
RT1425A  
RT1460A  
RT14100A  
Capacity  
System Gates  
Logic Gates  
ASIC Equivalent Gates  
PLD Equivalent Gates  
TTL Equivalent Package  
20-Pin PAL Equivalent Packages  
6,000  
4,000  
2,000  
5,000  
50  
24,000  
16,000  
8.000  
20,000  
200  
7,500  
5,000  
2,500  
6,250  
60  
18,000  
12,000  
6,000  
15.000  
150  
30,000  
20,000  
10,000  
25,000  
250  
20  
80  
25  
60  
100  
Logic Modules  
S-Modules  
C-Modules  
547  
N/A  
547  
1,232  
624  
608  
310  
160  
150  
848  
432  
416  
1,377  
697  
680  
User I/Os (Maximum)  
69  
20 MHz  
84  
140  
40 MHz  
172  
100  
60 MHz  
132  
168  
60 MHz  
196  
228  
60 MHz  
256  
Performance  
System Speed (Maximum)  
Packages (by Pin Count)  
CQFP  
Oct o b e r 2004  
i
© 2004 Actel Corporation  
See Actels website for the latest version of the datasheet  

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