Datasheet > RM9122

RM9122

更新时间： 2024-10-30 15:49:47

品牌	Logo	应用领域
美高森美 - MICROSEMI		/
页数	文件大小	规格书
2页	41K
描述
Microprocessor,

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中文翻译

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技术参数
数据手册

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RM9122 技术参数

生命周期：	Not Recommended	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.64
湿度敏感等级：	3	Base Number Matches：	1

RM9122 数据手册

RM9122

Released

RM9122 Integrated Microprocessor

• Provides a fully associative 64-entry

TLB with dual pages.

• Supports multiple reads with out-of-

order return.

• Provides a high-performance Floating

Point Unit (IEEE 754).

NETWORKING INTERFACES

FEATURES

• Provides a 32-bit 33/66 MHz PCI

interface compliant with the PCI 2.1

standard.

• Provides 2 Ethernet MAC or Generic

Packet Interfaces:

The RM9122 microprocessor integrates

high-speed memory and I/O interfaces to

create low latency accesses to main

memory and high bandwidth to I/O

devices. The RM9122 provides:

• Supports fixed-point DSP instructions.

•

Ethernet MAC interfaces support

standards-based TBI (1000 Mbps),

GMII (1000 Mbps) and MII (10/100

Mbps) interface modes.

• A CPU core compatible with the

MIPS64™ Instruction Set Architecture.

• High-speed integrated DDR SDRAM,

Local Bus, PCI, and Ethernet MAC

interfaces. Option to bypass the

Ethernet MAC interface to provide a

high-speed Generic Packet Interface.

• An 672-pin FCBGA package,

27 x 27 mm

I/O COHERENCY

• Supports full hardware I/O coherency

over the PCI and Ethernet MAC/GPI

networking interfaces allowing I/O

devices access to coherent memory.

• Provides Direct Deposit Cache mode

allowing the DMA of packet headers

directly into L2 cache from PCI,

Ethernet MAC, and Generic Packet

interfaces.

Generic Packet Interface supports

8-bit and 16-bit operation at 104

MHz using LVTTL I/O levels or at

208 MHz using HSTL I/O levels.

Dedicated multi-channel DMA for

Ethernet MAC/GPI interfaces

1 GHZ CPU CORE

• Provides a dual issue superscalar 7-

stage pipeline.

• Provides 16-Kbyte, 4-way set

associative L1 Instruction and Data

caches.

• Provides a 33 MHz Local Bus interface

for connectivity to boot-up and control

devices.

160 Gbps MULTI-PORT PACKET

SWITCH

• Connects processor to memory and

I/O interfaces.

• Supports 16550-like DUART and 2BI.

ADDITIONAL FEATURES

• Provides 8 Kbytes integrated low

latency scratch RAM.

• Provides an integrated on-chip EJTAG

Debug module to ensure easy

debugging of hardware and software

and a Trace Buffer to allow tracing

instruction execution for debugging.

• Provides a flexible 4-channel DMA

control architecture providing DMA to

• Supports simultaneous transfers on all

ports.

• Provides a 256 Kbyte, 4-way set

associative L2 cache with determinstic

access time for highest performance.

L2 cache is ECC protected.

• Provides Fast Packet Cache™ mode

to assist packet data processing.

• Provides an 8K entry branch prediction

table.

200 MHZ MEMORY CONTROLLER

• Supports 25.6 Gbps memory.

• Supports DDR SDRAM options.

• Supports 2 Gbytes using 512 Mbit

SDRAM and 4 Gbytes using 1 Gbit

SDRAM.

BLOCK DIAGRAM

1 GHz

E9000 Processor

EJTAG

Debug

256 Kbyte

L2 Cache

8 Kbyte

Integrated

RAM

GE+

FIFO

DMA

MII

GMII

TBI

DDR SDRAM

Controller

Packet Switch

FIFO

DMA

Controller

DUART/2BI

Timers

Local Bus

Controller

32-bit PCI

Controller

Microprocessor

Interrupt

Controller

PMC-2031706

Issue 3

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC.,

AND FOR ITS CUSTOMERS’ INTERNAL USE

中文翻译

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