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RM44L520

更新时间: 2024-10-31 11:07:55
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德州仪器 - TI 闪存
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165页 9371K
描述
16/32 位 RISC 闪存 MCU,Arm Cortex-R4F

RM44L520 数据手册

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RM44L920, RM44L520  
SPNS229C OCTOBER 2014REVISED NOVEMBER 2016  
RM44Lx20 16- and 32-Bit RISC Flash Microcontroller  
1 Device Overview  
1.1 Features  
1
• High-Performance Microcontroller (MCU) for  
Safety-Critical Applications  
• Enhanced Timing Peripherals  
– 7 Enhanced Pulse Width Modulator (ePWM)  
Modules  
– 6 Enhanced Capture (eCAP) Modules  
– Dual CPUs Running in Lockstep  
– ECC on Flash and RAM Interfaces  
– Built-In Self-Test (BIST) for CPU and On-chip  
RAMs  
– 2 Enhanced Quadrature Encoder Pulse (eQEP)  
Modules  
– Error Signaling Module With Error Pin  
– Voltage and Clock Monitoring  
• Two Next Generation High-End Timer (N2HET)  
Modules  
• ARM® Cortex®-R4F 32-Bit RISC CPU  
– 1.66 DMIPS/MHz With 8-Stage Pipeline  
– FPU With Single and Double Precision  
– 12-Region Memory Protection Unit (MPU)  
– Open Architecture With Third-Party Support  
• Operating Conditions  
– N2HET1: 32 Programmable Channels  
– N2HET2: 18 Programmable Channels  
– 160-Word Instruction RAM With Parity  
Protection Each  
– Each N2HET Includes Hardware Angle  
Generator  
– Dedicated High-End Timer Transfer Unit (HTU)  
for Each N2HET  
– Up to 180-MHz System Clock  
– Core Supply Voltage (VCC): 1.14 to 1.32 V  
– I/O Supply Voltage (VCCIO): 3.0 to 3.6 V  
• Integrated Memory  
• Two 12-Bit Multibuffered ADC Modules  
– ADC1: 24 Channels  
– ADC2: 16 Channels  
– 16 Shared Channels  
– 64 Result Buffers With Parity Protection Each  
• Multiple Communication Interfaces  
– Up to Three CAN Controllers (DCANs)  
– 64 Mailboxes With Parity Protection Each  
– Up to 1MB of Flash With ECC  
– 128KB of RAM With ECC  
– 64KB of Flash for Emulated EEPROM With  
ECC  
• Common Platform Architecture  
– Consistent Memory Map Across Family  
– Real-Time Interrupt Timer (RTI) OS Timer  
– 128-Channel Vectored Interrupt Module (VIM)  
– 2-Channel Cyclic Redundancy Checker (CRC)  
• Direct Memory Access (DMA) Controller  
– 16 Channels and 32 Peripheral Requests  
– Parity for Control Packet RAM  
– DMA Accesses Protected by Dedicated MPU  
• Frequency-Modulated Phase-Locked Loop  
(FMPLL) With Built-In Slip Detector  
• IEEE 1149.1 JTAG, Boundary Scan and ARM  
CoreSight™ Components  
– Compliant to CAN Protocol Version 2.0A and  
2.0B  
– Inter-Integrated Circuit (I2C)  
– 3 Multibuffered Serial Peripheral Interfaces  
(MibSPIs)  
– 128 Words With Parity Protection Each  
– 8 Transfer Groups  
– One Standard Serial Peripheral Interface (SPI)  
Module  
– Two UART (SCI) Interfaces, One With Local  
Interconnect Network (LIN 2.1) Interface  
Support  
• Advanced JTAG Security Module (AJSM)  
• Up to 64 General-Purpose I/O (GIO) Pins  
• Packages  
– 144-Pin Quad Flatpack (PGE) [Green]  
– 100-Pin Quad Flatpack (PZ) [Green]  
– Up to 16 GIO Pins With Interrupt Generation  
Capability  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 
 

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