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RHRXH162374K-01Q PDF预览

RHRXH162374K-01Q

更新时间: 2024-11-28 03:01:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器
页数 文件大小 规格书
17页 513K
描述
Rad hard low voltage CMOS 16-bit D-type Flip-Flop with 3.6V tolerant inputs and outputs

RHRXH162374K-01Q 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DFP
包装说明:DFP, FL48,.4,25针数:48
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.31系列:ALVC/VCX/A
JESD-30 代码:R-CDFP-F48JESD-609代码:e0
长度:15.75 mm负载电容(CL):30 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:190000000 Hz
最大I(ol):0.008 A位数:8
功能数量:2端口数量:2
端子数量:48最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE WITH SERIES RESISTOR
输出极性:TRUE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DFP封装等效代码:FL48,.4,25
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/3.3 V
Prop。Delay @ Nom-Sup:5.5 ns传播延迟(tpd):6.2 ns
认证状态:Not Qualified筛选级别:MIL-PRF-38535 Class Q
座面最大高度:2.72 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.8 V
标称供电电压 (Vsup):2.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:FLAT
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED总剂量:100k Rad(Si) V
触发器类型:POSITIVE EDGE宽度:9.65 mm
Base Number Matches:1

RHRXH162374K-01Q 数据手册

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54VCXH162374  
Rad hard low voltage CMOS 16-bit D-type Flip-Flop (3-state)  
with 3.6V tolerant inputs and outputs  
Features  
1.65 to 3.6V inputs and outputs  
High speed:  
– t = 3.4ns (Max) at V = 3.0 to 3.6V  
PD  
CC  
– t = 4.8ns (Max) at V = 2.3 to 2.7V  
PD  
CC  
Symmetrical impedance outputs:  
– |I | = I = 12mA (Min) at V = 3.0V  
Flat-48  
OH  
OL  
CC  
– |I | = I = 8mA (Min) at V = 2.3V  
OH  
OL  
CC  
Description  
Power down protection on inputs and outputs  
26serie resistors in outputs  
The 54VCXH162374 is a low voltage CMOS 16  
bit d-type Flip-Flop with 3 state outputs non  
inverting fabricated with sub-micron silicon gate  
Operating voltage range:  
– V (Opr) = 1.65V to 3.6V  
CC  
2
and five-layer metal wiring C MOS technology. It  
Pin and function compatible with 54 SERIES  
is ideal for low power and very high speed 1.65 to  
3.6V applications; it can be interfaced to 3.6V  
signal environment for both inputs and outputs.  
H162374  
Bus hold provided on both sides  
Cold spare function  
These 16 bit D-TYPE flip-flops are controlled by  
two clock inputs (nCK) and two output enable  
inputs (nOE).  
Latch-up performance exceeds  
300mA (JESD 17)  
ESD performance:  
On the positive transition of the (nCK), the nQ  
outputs will be set to the logic state that were  
setup at the nD inputs.  
– HBM > 2000V  
(MIL STD 883 method 3015); MM > 200V  
300KRad Mil1019.6 Condition A, (RHA QML  
While the (nOE) input is low, the 8 outputs (nQ)  
will be in a normal state (HIGH or LOW logic level)  
and while high level the outputs will be in a high  
impedance state.  
qualification extension undergone)  
No SEL, no SEU under 72 Mev/cm2/mg LET  
heavy ions irradiation  
Any output control does not affect the internal  
operation of flip flops; that is, the old data can be  
retained or the new data can be entered even  
while the outputs are OFF.  
QML qualified product  
Device fully compliant with  
DSCC SMD 5962-05212  
July 2007  
Rev 4  
1/17  
www.st.com  
17  

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