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RHRXH162374K01V PDF预览

RHRXH162374K01V

更新时间: 2024-11-28 15:49:39
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 驱动输出元件逻辑集成电路
页数 文件大小 规格书
18页 494K
描述
ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, CDFP48, CERAMIC, DFP-48

RHRXH162374K01V 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:DFP
包装说明:CERAMIC, DFP-48针数:48
Reach Compliance Code:compliant风险等级:5.31
系列:ALVC/VCX/AJESD-30 代码:R-CDFP-F48
JESD-609代码:e0长度:15.75 mm
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:2端口数量:2
端子数量:48最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE WITH SERIES RESISTOR
输出极性:TRUE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DFP封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):6.2 ns认证状态:Not Qualified
筛选级别:MIL-PRF-38535 Class V座面最大高度:2.72 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.8 V
标称供电电压 (Vsup):2.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:TIN LEAD端子形式:FLAT
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED总剂量:100k Rad(Si) V
宽度:9.65 mmBase Number Matches:1

RHRXH162374K01V 数据手册

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54VCXH162374  
Rad hard low voltage CMOS 16-bit d-type flip-flop (3-state)  
with 3.6 V tolerant inputs and outputs  
Features  
1.65 to 3.6 V inputs and outputs  
High speed:  
– t = 3.4 ns (Max.) at V = 3.0 to 3.6 V  
PD  
CC  
– t = 4.8 ns (Max.) at V = 2.3 to 2.7 V  
PD  
CC  
Symmetrical impedance outputs:  
– |I | = I = 12 mA (Min.) at V = 3.0 V  
Flat-48  
OH  
OL  
CC  
– |I | = I = 8 mA (Min.) at V = 2.3 V  
OH  
OL  
CC  
Description  
Power down protection on inputs and outputs  
26Ω serie resistors in outputs  
The 54VCXH162374 is a low voltage CMOS 16  
bit d-type flip-flop with 3 state outputs non  
inverting fabricated with sub-micron silicon gate  
Operating voltage range:  
– V (Opr) = 1.65 V to 3.6 V  
CC  
2
and five-layer metal wiring C MOS technology. It  
Pin and function compatible with 54 series  
is ideal for low power and very high speed 1.65 to  
3.6 V applications; it can be interfaced to 3.6 V  
signal environment for both inputs and outputs.  
H162374  
Bus hold provided on both sides  
Cold spare function  
These 16 bit d-type flip-flops are controlled by two  
clock inputs (nCK) and two output enable inputs  
(nOE).  
Latch-up performance exceeds  
300 mA (JESD 17)  
ESD performance:  
On the positive transition of the (nCK), the nQ  
outputs will be set to the logic state that were  
setup at the nD inputs.  
– HBM > 2000 V  
(MIL STD 883 method 3015); MM > 200 V  
300KRad Mil1019.6 condition A, (RHA QML  
While the (nOE) input is low, the 8 outputs (nQ)  
will be in a normal state (HIGH or LOW logic level)  
and while high level the outputs will be in a high  
impedance state.  
qualification extension undergone)  
No SEL, no SEU and no SET under 110  
Mev/cm2/mg LET heavy ions irradiation  
Any output control does not affect the internal  
operation of flip flops; that is, the old data can be  
retained or the new data can be entered even  
while the outputs are OFF.  
QML qualified product  
Device fully compliant with  
DSCC SMD 5962-05212  
100 mV typical input hysteresis  
September 2009  
Doc ID 10654 Rev 6  
1/18  
www.st.com  
18  

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