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QS53806ASO8 PDF预览

QS53806ASO8

更新时间: 2024-10-27 20:09:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
6页 95K
描述
Low Skew Clock Driver, 0 True Output(s), 5 Inverted Output(s), CMOS, PDSO20, SOIC-20

QS53806ASO8 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.7输入调节:SCHMITT TRIGGER
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:2反相输出次数:5
端子数量:20实输出次数:
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):5.8 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.8 ns
座面最大高度:2.65 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

QS53806ASO8 数据手册

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GUARANTEED LOW SKEW  
QS53806/A  
3.3V CMOS CLOCK  
DRIVER/BUFFER  
FEATURES  
DESCRIPTION  
JEDEC compatible LVTTL inputs and outputs  
10 low skew clock outputs (inverting)  
Monitor output  
TheQS53806clockdriver/buffercircuitcanbeusedforclockbuffering  
schemes where low skew is a key parameter. The QS53806 offers two  
banks of five inverting outputs. Designed in IDT's proprietary CMOS  
process,these devices provide lowpropagationdelaybufferingwithon-  
chipskewof0.6ns forsame-transition,same-banksignals.  
Clock inputs are 5V tolerant  
Pinout and function compatible with QS5806  
Input hysteresis for better noise margin  
Guaranteed low skew  
0.6ns output skew (same bank)  
0.8ns output skew (different banks)  
1.5ns part-to-part skew  
Std. and A speed grades  
Available in QSOP and SOIC packages  
FUNCTIONALBLOCKDIAGRAM  
OEA  
INA  
5
OA5 - OA1  
MON  
5
INB  
OB5 - OB1  
OEB  
INDUSTRIAL TEMPERATURE RANGE  
JULY 2000  
1
c
1999 Integrated Device Technology, Inc.  
DSC-5828/-  

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