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QS34XST257Q3 PDF预览

QS34XST257Q3

更新时间: 2024-11-23 15:48:55
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管逻辑集成电路
页数 文件大小 规格书
10页 127K
描述
Multiplexer And Demux/Decoder, CBT/FST/QS/5C/B Series, 16-Func, 2 Line Input, 1 Line Output, True Output, CMOS, PDSO80, MILLIPAK, DIP-80

QS34XST257Q3 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC针数:80
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.78系列:CBT/FST/QS/5C/B
JESD-30 代码:R-PDSO-G80JESD-609代码:e0
逻辑集成电路类型:MULTIPLEXER AND DEMUX/DECODER功能数量:16
输入次数:2输出次数:1
端子数量:80最高工作温度:85 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP80,.25,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
子类别:Other Logic ICs最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

QS34XST257Q3 数据手册

 浏览型号QS34XST257Q3的Datasheet PDF文件第2页浏览型号QS34XST257Q3的Datasheet PDF文件第3页浏览型号QS34XST257Q3的Datasheet PDF文件第4页浏览型号QS34XST257Q3的Datasheet PDF文件第5页浏览型号QS34XST257Q3的Datasheet PDF文件第6页浏览型号QS34XST257Q3的Datasheet PDF文件第7页 
QUICKSWITCH® PRODUCTS  
IDTQS34XST257  
HIGH-SPEED CMOS  
SYNCHROSWITCH™ 32:16 MUX/  
DEMUX WITH ACTIVE TERMINATORS  
FEATURES:  
DESCRIPTION:  
Enhanced N channel FET with no inherent diode to Vcc  
Bidirectional signal flow  
Flow-through pinout  
Zero propagation delay, zero ground bounce  
16 banks of 2:1 Mux/Demux  
Port select synchronous to the clock  
Clock enable and Asynchronous enable  
“Bus-hold” terminators on the Demux side  
Undershoot clamp diodes on all switch and control pins  
Asynchronous SEL option  
The QS34XST257 is a high-speed CMOS quad 32:16 multiplexer/  
demultiplexerwithactiveterminators(bus-holdcircuits)onthedemuxside.  
It is organized as four independent quad 2:1 mux/demux blocks. Port  
selectionandconnection, controlledbySELsignals, canbe eitherasyn-  
chronous orsynchronous. Inthe synchronous mode, the AorBporttoY  
portconnectionis updatedontherisingedgeoftheinputclockCLK. Once  
the port-to-portconnectionis made,data flowcanbe bi-directionalwitha  
typical 250ps propagation delay through the switch. Clock Enable,  
overriding Asynchronous Enable, and Asynchronous Select controls  
provide additionaldesignflexibility.  
Break-before-make feature  
The bus-hold circuits latch the last data driven on the demux side,  
providinginfiniteholdtimeandglitch-freesignaltransitions. Synchronous  
controlsandbus-holdeasetimingconstraintsinmanyhighspeeddatamux/  
demux applications, such as bank interleaving. The QS34XST257 is  
available inthe space-saving,80-pindual-in-line MillipaQpackage.  
Available in 80-pin MillipaQ (Q3)  
Bus-hold eliminates floating bus lines and reduces static power  
consumption  
APPLICATIONS:  
The QS34XST257 is characterized for operation at -40°C to +85°C.  
Memory Interleaving  
FUNCTIONALBLOCKDIAGRAM  
R
=
T
SELn  
CLKn  
CONTROL  
CLKENn  
LOGIC  
OEn  
SYNCn  
An0  
Bn0  
An1  
Bn1  
An2  
Bn2  
An3  
Bn3  
T
T
T
T
T
T
T
T
Yn0  
Yn1  
Yn2  
Yn3  
NOTE: One of four blocks shown.  
INDUSTRIAL TEMPERATURE RANGE  
NOVEMBER 1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-5532/-  

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