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QS34XS257Q3G PDF预览

QS34XS257Q3G

更新时间: 2024-11-19 19:47:35
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
9页 73K
描述
Logic Circuit, CMOS, PDSO80

QS34XS257Q3G 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:SSOP, SSOP80,.25,20Reach Compliance Code:compliant
风险等级:5.84JESD-30 代码:R-PDSO-G80
端子数量:80最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP80,.25,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
电源:5 V认证状态:Not Qualified
子类别:Other Logic ICs标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
Base Number Matches:1

QS34XS257Q3G 数据手册

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QUICKSWITCH® PRODUCTS  
IDTQS34XS257  
HIGH-SPEED CMOS  
SYNCHROSWITCH™  
32:16 MUX/DEMUX  
DESCRIPTION:  
FEATURES:  
The QS34XS257 is a high-speed CMOS quad 32:16 multiplexer/  
demultiplexer. It is organized as four independent quad 2:1 mux/demux  
blocks. Portselectionandconnection, controlledbySELsignals, canbe  
eitherasynchronous orsynchronous. Inthe synchronous mode, the Aor  
BporttoYportconnectionis updatedonthe risingedge ofthe inputclock  
CLK. Once the port-to-port connection is made, data flow can be bi-  
directionalwithatypical250pspropagationdelaythroughtheswitch. Clock  
Enable,overridingAsynchronous Enable,andAsynchronous Selectcon-  
trols provideadditionaldesignflexibility.  
• Enhanced N channel FET with no inherent diode to Vcc  
• Bidirectional signal flow  
• Flow-through pinout  
Zero propagation delay, zero ground bounce  
• 16 banks of 2:1 Mux/Demux  
• Port select synchronous to the clock  
• Clock enable and asynchronous enable  
Undershoot clamp diodes on all switch and control inputs  
Asynchronous SEL option  
Synchronous controls easetimingconstraints inmanyhighspeeddata  
mux/demuxapplications, suchas bankinterleaving. The QS34XS257is  
available inthe space-saving,80-pindual-in-line MillipaQpackage.  
The QS34XS257 is characterized for operation at -40°C to +85°C.  
• Break-before-make feature  
• Bus-hold eliminates floating bus lines and reduces static power  
consumption  
Available in 80-pin Millipaq package  
APPLICATIONS:  
Memory interleaving  
FUNCTIONALBLOCKDIAGRAM  
SELn  
CLKn  
CONTROL  
CLKENn  
LOGIC  
OEn  
SYNCn  
An0  
Bn0  
An1  
Bn1  
An2  
Bn2  
An3  
Bn3  
Yn0  
Yn1  
Yn2  
Yn3  
NOTE:  
1. One of four blocks shown.  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JUNE 2006  
1
c
2006 Integrated Device Technology, Inc.  
DSC-5578/3  

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